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CN-120017044-B - Binary ternary circuit

CN120017044BCN 120017044 BCN120017044 BCN 120017044BCN-120017044-B

Abstract

The present disclosure provides a two-wire ternary circuit. The binary circuit is used for carrying out ternary operation and comprises two line input ends, wherein the number of the two line input ends is more than one, each two line input end comprises a high line input end for inputting a high line input signal and a low line input end for inputting a low line input signal, the high line input signal and the low line input signal are respectively one of a high level signal and a low level signal, the number of the two line output ends is one and comprises a high line output end for outputting a high line output signal and a low line output end for outputting a low line output signal, the high line output signal and the low line output signal are respectively one of a high level signal and a low level signal, and the high line output end and the low line output end are respectively connected with the output of two binary logic gates, or are respectively connected with the output of one binary logic gate, one of the high line input end and the low line input end, or are respectively connected with the low line input end and the high line input end.

Inventors

  • WEI NAN

Assignees

  • 北京大学
  • 北京元芯碳基集成电路研究院

Dates

Publication Date
20260512
Application Date
20250122

Claims (16)

  1. 1. A two-wire ternary circuit, which comprises a first circuit and a second circuit, the binary line ternary circuit is used for performing ternary operation and is characterized by comprising the following components: Two-wire input terminals, the number of the two-wire input terminals is more than one, each two-wire input terminal respectively comprises a high-wire input terminal for inputting a high-wire input signal and a low-wire input terminal for inputting a low-wire input signal, the high-wire input signal and the low-wire input signal are respectively one of a high-level signal and a low-level signal, and A binary line output end, wherein the number of the binary line output ends is one and comprises a high line output end for outputting a high line output signal and a low line output end for outputting a low line output signal, the high line output signal and the low line output signal are respectively one of the high level signal and the low level signal, the high line output end and the low line output end are respectively connected with the output of two binary logic gates, or respectively connected with the output of one binary logic gate and one input end of a high line input end and a low line input end, or respectively connected with the low line input end and the high line input end, The binary circuit can be used for operation in a high-resistance state, wherein when the high-line input signal is a low-level signal and the low-line input signal is a high-level signal, the binary signal of the binary circuit is in a first state, when the high-line input signal is a high-level signal and the low-line input signal is a low-level signal, the binary signal of the binary circuit is in a second state, when the high-line input signal and the low-line input signal are the same-level signal, the binary signal of the binary circuit is in one of a third state and a high-resistance state, and when the same-level signal is a low-level signal, the binary signal of the binary circuit is in the other of the third state and the high-resistance state.
  2. 2. The two-wire ternary circuit of claim 1, further comprising: And the number of the binary logic gates is one or more, and at least one part of the binary logic gates are connected with at least one input end of the high-line input end and the low-line input end.
  3. 3. The two-wire ternary circuit of claim 1, wherein the two-wire ternary circuit is an inverter circuit, The number of the two-wire input ends and the number of the two-wire output ends are respectively one, wherein the high-wire input ends and the low-wire input ends of the two-wire input ends are staggered, and the low-wire output ends and the high-wire output ends of the two-wire output ends are respectively connected.
  4. 4. The two-wire ternary circuit of claim 2, wherein the two-wire ternary circuit is a NAND gate circuit, The binary logic gate comprises a NAND gate, a NOR gate, a first inverter and a second inverter, the number of the two-wire input ends is two, the high-wire input end of the first two-wire input end is connected with one input of the NAND gate, the low-wire input end of the first two-wire input end is connected with one input of the NOR gate, the high-wire input end of the second two-wire input end is connected with the other input of the NAND gate, the low-wire input end of the second two-wire input end is connected with the other input of the NOR gate, the output of the NAND gate and the output of the NOR gate are respectively connected with the input of the first inverter and the input of the second inverter, the outputs of the first inverter and the second inverter are staggered, and a low-wire output signal and a high-wire output signal are respectively output.
  5. 5. The two-wire ternary circuit of claim 2, wherein the two-wire ternary circuit is an AND gate circuit, The binary logic gate comprises a NAND gate, a NOR gate, a first inverter and a second inverter, the number of the two-wire input ends is two, the high-wire input end of the first two-wire input end is connected with one input of the NAND gate, the low-wire input end of the first two-wire input end is connected with one input of the NOR gate, the high-wire input end of the second two-wire input end is connected with the other input of the NAND gate, the low-wire input end of the second two-wire input end is connected with the other input of the NOR gate, the output of the NAND gate and the output of the NOR gate are respectively connected with the input of the first inverter and the input of the second inverter, the output of the first inverter and the output of the second inverter are not staggered, and a high-wire output signal and a low-wire output signal are respectively output.
  6. 6. The two-wire ternary circuit of claim 2, wherein the two-wire ternary circuit is a NOR gate, The binary logic gate comprises a NOR gate, a NAND gate, a first inverter and a second inverter, the number of the two-wire input ends is two, the high-wire input end of the first two-wire input end is connected with one input of the NOR gate, the low-wire input end of the first two-wire input end is connected with one input of the NAND gate, the high-wire input end of the second two-wire input end is connected with the other input of the NOR gate, the low-wire input end of the second two-wire input end is connected with the other input of the NAND gate, the output of the NOR gate and the output of the NAND gate are respectively connected with the input of the first inverter and the input of the second inverter, the outputs of the first inverter and the second inverter are staggered, and a low-wire output signal and a high-wire output signal are respectively output.
  7. 7. The two-wire ternary circuit of claim 2, wherein the two-wire ternary circuit is an OR gate, The binary logic gate comprises a NOR gate, a NAND gate, a first inverter and a second inverter, the number of the two-wire input ends is two, the high-wire input end of the first two-wire input end is connected with one input of the NOR gate, the low-wire input end of the first two-wire input end is connected with one input of the NAND gate, the high-wire input end of the second two-wire input end is connected with the other input of the NOR gate, the low-wire input end of the second two-wire input end is connected with the other input of the NAND gate, the output of the NOR gate and the output of the NAND gate are respectively connected with the input of the first inverter and the input of the second inverter, the output of the first inverter and the output of the second inverter are not staggered, and a high-wire output signal and a low-wire output signal are respectively output.
  8. 8. The two-wire ternary circuit of claim 2, wherein the two-wire ternary circuit is a self-increasing gate circuit, The binary logic gate comprises NOR gates, the number of the two-wire input ends is one, the high-wire input end of the two-wire input end is connected with one input of the NOR gate, the low-wire input end of the two-wire input end is connected with the other input of the NOR gate, the NOR gate outputs a high-wire output signal, and the low-wire output signal is a high-wire input signal of the high-wire input end.
  9. 9. The two-wire ternary circuit of claim 2, wherein the two-wire ternary circuit is a self-subtracting gate, The binary logic gate comprises NOR gates, the number of the two-wire input ends is one, the high-wire input end of the two-wire input end is connected with one input of the NOR gate, the low-wire input end of the two-wire input end is connected with the other input of the NOR gate, the NOR gate outputs a low-wire output signal, and the high-wire output signal is a low-wire input signal of the low-wire input end.
  10. 10. The two-wire ternary circuit of claim 2, wherein the two-wire ternary circuit is an inverter circuit, The binary logic gate comprises a first inverter and a second inverter, the number of the two-line input ends is one, the high-line input end and the low-line input end of the two-line input end are respectively connected with the input of the first inverter and the input of the second inverter, the output of the first inverter and the output of the second inverter are staggered, and a low-line output signal and a high-line output signal are respectively output.
  11. 11. The two-wire ternary circuit of claim 2, wherein the two-wire ternary circuit is a NAND gate circuit, The binary logic gate comprises a first NAND gate and a second NAND gate, the number of the two-wire input ends is two, the high-wire input end of the first two-wire input end is connected with one input of the first NAND gate, the high-wire input end of the second two-wire input end is connected with the other input of the first NAND gate, the low-wire input end of the first two-wire input end is connected with one input of the second NAND gate, the low-wire input end of the second two-wire input end is connected with the other input of the second NAND gate, the output of the first NAND gate and the output of the second NAND gate are staggered, and a low-wire output signal and a high-wire output signal are respectively output.
  12. 12. The two-wire ternary circuit of claim 2, wherein the two-wire ternary circuit is an AND gate circuit, The binary logic gate comprises a first NAND gate, a second NAND gate, a first inverter and a second inverter, the number of the two-wire input ends is two, the high-wire input end of the first two-wire input end is connected with one input of the first NAND gate, the high-wire input end of the second two-wire input end is connected with the other input of the first NAND gate, the low-wire input end of the first two-wire input end is connected with one input of the second NAND gate, the low-wire input end of the second two-wire input end is connected with the other input of the second NAND gate, the output of the first NAND gate and the output of the second NAND gate are respectively connected with the input of the first inverter and the input of the second inverter, the output of the first inverter and the output of the second inverter are not staggered, and the high-wire output signal and the low-wire output signal are respectively output.
  13. 13. The two-wire ternary circuit of claim 2, wherein the two-wire ternary circuit is a NOR gate, The binary logic gate comprises a first NOR gate and a second NOR gate, the number of the two-wire input ends is two, the high-wire input end of the first two-wire input end is connected with one input of the first NOR gate, the high-wire input end of the second two-wire input end is connected with the other input of the first NOR gate, the low-wire input end of the first two-wire input end is connected with one input of the second NOR gate, the low-wire input end of the second two-wire input end is connected with the other input of the second NOR gate, the output of the first NOR gate and the output of the second NOR gate are staggered, and a low-wire output signal and a high-wire output signal are respectively output.
  14. 14. The two-wire ternary circuit of claim 2, wherein the two-wire ternary circuit is an OR gate, The binary logic gate comprises a first NOR gate, a second NOR gate, a first inverter and a second inverter, the number of the two-wire input ends is two, the high-wire input end of the first two-wire input end is connected with one input of the first NOR gate, the high-wire input end of the second two-wire input end is connected with the other input of the first NOR gate, the low-wire input end of the first two-wire input end is connected with one input of the second NOR gate, the low-wire input end of the second two-wire input end is connected with the other input of the second NOR gate, the output of the first NOR gate and the output of the second NOR gate are respectively connected with the input of the first inverter and the input of the second inverter, the output of the first inverter and the output of the second inverter are not staggered, and high-wire output signals and low-wire output signals are respectively output.
  15. 15. The two-wire ternary circuit of claim 2, wherein the two-wire ternary circuit is a self-increasing gate circuit, The binary logic gate comprises an inverter, a NOR gate and a NAND gate, the number of the two-wire input ends is one, the high-wire input end of the two-wire input end is connected with one input of the NOR gate and one input of the NAND gate, the low-wire input end of the two-wire input end is connected with the input of the inverter and the other input of the NAND gate, the output of the inverter is connected with the other input of the NOR gate, and the NOR gate and the NAND gate respectively output high-wire output signals and low-wire output signals.
  16. 16. The two-wire ternary circuit of claim 2, wherein the two-wire ternary circuit is a self-subtracting gate, The binary logic gate comprises an inverter, a NOR gate and a NAND gate, the number of the two-wire input ends is one, the high-wire input end of the two-wire input end is connected with one input of the NOR gate and one input of the inverter, the output of the inverter is connected with one input of the NAND gate, the low-wire input end of the two-wire input end is connected with the other input of the NOR gate and the other input of the NAND gate, and the NOR gate and the NAND gate respectively output high-wire output signals and low-wire output signals.

Description

Binary ternary circuit Technical Field The present disclosure relates to a two-wire ternary circuit. Background In a ternary circuit, ternary operations are performed by three state signals, for example, by 0, 1,2, and the like. In existing ternary circuits, the noise margin is low (three levels need to be considered), the TFET implementation speed is low and currently difficult to have a chip implementation, and is not sufficient for efficient operation. And the single line shows non-parallelism, which results in low symmetry of the circuit and the need to introduce complement, dislocation and other fragmental situations. In addition, in the current ternary circuit, it is difficult to implement the operation in a special state (such as a high resistance state). For example, GPIO ports typically exist in three forms of high level, low level and high resistance, and existing ternary circuits cannot implement high resistance operation, and binary circuits cannot implement high resistance operation. Disclosure of Invention The present disclosure provides a two-wire ternary circuit. According to one aspect of the disclosure, a binary circuit is provided for performing a ternary operation, and includes two-wire inputs, the number of which is one or more, each of which includes a high-wire input to which a high-wire input signal is input and a low-wire input to which a low-wire input signal is input, the high-wire input signal and the low-wire input signal being one of a high-level signal and a low-level signal, respectively, and two-wire outputs, the number of which is one and includes a high-wire output to which a high-wire output signal is output and a low-wire output to which a low-wire output signal is output, the high-wire output signal and the low-wire output signal being one of the high-level signal and the low-level signal, respectively, the high-wire output and the low-wire output being connected to outputs of two binary logic gates, respectively, or being connected to one of a high-wire input and a low-wire input, respectively, or being connected to the high-wire input and the high-wire input, respectively. The binary circuit according to one embodiment of the present disclosure further comprises a number of binary logic gates, one or more, at least a portion of the binary logic gates having inputs connected to at least one of the high line input and the low line input. According to the binary circuit according to one embodiment of the present disclosure, the binary circuit is an inverter circuit, and the number of the two-wire input terminals and the number of the two-wire output terminals are respectively one, wherein the high-wire input terminals and the low-wire input terminals of the two-wire input terminals are staggered, and are respectively connected with the low-wire output terminals and the high-wire output terminals of the two-wire output terminals. According to the binary circuit of one embodiment of the disclosure, the binary circuit is a nand gate circuit, the binary logic gate comprises a nand gate, a nor gate, a first inverter and a second inverter, the number of the two line input ends is two, the high line input end of the first two line input end is connected with one input of the nand gate, the low line input end of the first two line input end is connected with one input of the nor gate, the high line input end of the second two line input end is connected with the other input of the nand gate, the low line input end of the second two line input end is connected with the other input of the nor gate, the output of the nand gate and the output of the nor gate are respectively connected with the input of the first inverter and the input of the second inverter, the outputs of the first inverter and the second inverter are staggered, and a low line output signal and a high line output signal are respectively output. According to the binary circuit of one embodiment of the disclosure, the binary circuit is an and circuit, the binary logic gate comprises a nand gate, a nor gate, a first inverter and a second inverter, the number of the two line inputs is two, the high line input end of the first two line input end is connected with one input of the nand gate, the low line input end of the first two line input end is connected with one input of the nor gate, the high line input end of the second two line input end is connected with the other input of the nand gate, the low line input end of the second two line input end is connected with the other input of the nor gate, the output of the nand gate and the output of the nor gate are respectively connected with the inputs of the first inverter and the second inverter, the outputs of the first inverter and the second inverter are not staggered, and respectively output high line output signals and low line output signals. According to the binary circuit of one embodiment of the disclosure, the binary circuit is a nor gate circuit, the binary l