CN-120085742-B - Power consumption inhibition method and device, electronic equipment and chip

Abstract

The disclosure relates to a power consumption suppression method, a device, electronic equipment and a chip, and relates to the technical field of integrated circuit power consumption management. The power consumption suppression method specifically comprises the steps of responding to the power supply limited risk of a power supply unit, determining respective load information of N processors, wherein N is an integer greater than or equal to 2, and performing power consumption suppression on the N processors according to the load information.

Inventors

• XIE LIQIAN

Assignees

• 北京玄戒技术有限公司

Dates

Publication Date

20260508

Application Date

20250212

Claims (18)

1. 1. The power consumption suppression method is characterized by belonging to the field of integrated circuit power consumption management, and comprises the following steps: The method comprises the steps of responding to the occurrence of a power supply limitation risk of a power supply unit, determining load information of N processors, wherein the load information comprises load priority, updating priority information of tasks before the N processors execute the tasks, sending the updated priority information to a load priority judging device through a hard wire, and sequencing according to the priority information and the load priority of the N processors from low to high to determine the load priority of the N processors, N is an integer greater than or equal to 2, wherein the determining process of the occurrence of the power supply limitation risk of the power supply unit comprises the steps of acquiring a first power consumption value of each processor, determining a total second power consumption value of the N processors according to the first power consumption value of each processor, acquiring a third power consumption value corresponding to the maximum power supply capacity of the power supply unit, and responding to the second power consumption value being greater than the third power consumption value, and determining the occurrence of the power supply limitation risk of the power supply unit; Performing power consumption inhibition on the N processors according to the load information; And responding to the power supply limited risk release of the power supply unit, determining the load priority of the power-suppressed processor in the N processors, sequencing the power-suppressed processors according to the load priority from high to low, acquiring a power consumption recovery sequence, and recovering the power consumption of the power-suppressed processor according to the power consumption recovery sequence, wherein the power recovery process comprises the steps of generating an up-conversion instruction for the power-suppressed processor, sending the up-conversion instruction to a clock frequency adjusting unit corresponding to the power-suppressed processor, and carrying out up-conversion processing on the power-suppressed processor based on the up-conversion instruction through the clock frequency adjusting unit.
2. 2. The method of claim 1, wherein the load information further comprises: At least one of monitoring temperature and monitoring power consumption information.
3. 3. The method of claim 1, wherein the obtaining a first power consumption value for each processor comprises: sampling the power consumption related characteristics of the processor to obtain a power consumption characteristic value of the processor; And performing power consumption calculation of the processor according to the power consumption characteristic value to obtain a first power consumption value of the processor.
4. 4. The method of claim 2, wherein said power consumption suppressing the N processors according to the load information comprises: Sequencing the N processors according to the sequence of the load priority from low to high, and acquiring a first power consumption inhibition sequence corresponding to the N processors; and performing power consumption inhibition on the N processors according to the first power consumption inhibition sequence until the power consumption inhibition ending condition is met.
5. 5. The method of claim 2, wherein the power consumption suppressing the N processors according to the load information further comprises: for any one of the monitored temperature and the monitored power consumption information, determining M first processors with early warning in the N processors according to the any one of the monitored temperature and the monitored power consumption information, wherein the early warning is related to the any one of the N processors, and M is an integer greater than or equal to 1; and performing power consumption inhibition on the M first processors until the power consumption inhibition ending condition is met.
6. 6. The method of claim 2, wherein the power consumption suppressing the N processors according to the load information further comprises: Determining the respective importance degrees of the monitoring temperature, the load priority and the monitoring power consumption information; Determining the information sequence for power consumption suppression corresponding to the monitored temperature, the load priority and the monitored power consumption information according to the importance degree; and performing power consumption suppression on the N processors based on the monitoring temperature, the load priority and the monitoring power consumption information according to the information sequence for power consumption suppression until a power consumption suppression ending condition is met.
7. 7. The method of claim 6, wherein the method further comprises: After power consumption inhibition is carried out on the N processors based on any information, judging whether the power supply unit still has a power supply limited risk or not; And responding to the power supply unit having the power supply limited risk, and continuing to use the next item of information to carry out power consumption inhibition on the N processors.
8. 8. The method of claim 2, wherein the power consumption suppressing the N processors according to the load information further comprises: combining the monitoring temperature, the load priority and the monitoring power consumption information to obtain at least one combination and a second power consumption inhibition sequence corresponding to the combination; And performing power consumption inhibition on the N processors according to the second power consumption inhibition sequence based on the information in the combination until a power consumption inhibition ending condition is met.
9. 9. The method of claim 8, wherein the method further comprises: for a first item of information in the monitored temperature and the monitored power consumption information, determining T second processors with early warning in the N processors according to the first item of information, wherein the early warning is related to the first item of information, and T is an integer greater than or equal to 1; Sequencing the T second processors according to the load priority from low to high to obtain a second power consumption suppression sequence; And performing power consumption suppression on the T second processors according to the second power consumption suppression sequence until the power consumption suppression ending condition is met.
10. 10. The method according to claim 9, wherein the method further comprises: after the power consumption of the T second processors is restrained, judging whether the power supply unit still has a power supply limited risk or not; responding to the power supply unit still having the power supply limited risk, and continuing to determine S third processors with early warning according to second information in the monitored temperature and the monitored power consumption information, wherein the early warning is related to the second information, and S is an integer greater than or equal to 1; sequencing the S third processors according to the load priority from low to high to obtain a third power consumption suppression sequence; and performing power consumption inhibition on the S third processors according to the third power consumption inhibition sequence until the power consumption adjustment ending condition is met.
11. 11. The method according to claim 9 or 10, characterized in that the method further comprises: Responding to the power supply unit still having the power supply limited risk, and sequencing the N processors according to the current load priorities of the N processors from low to high to obtain a fourth power consumption inhibition sequence; and performing power consumption inhibition on the N processors according to the fourth power consumption inhibition sequence until the power consumption adjustment ending condition is met.
12. 12. The method according to any one of claims 4-10, further comprising: acquiring second power consumption of the N processors after power consumption inhibition, and determining that the power consumption inhibition ending condition is met in response to the second power consumption after power consumption inhibition being smaller than the third power consumption value, or And determining that the processors meet the power consumption inhibition ending condition in response to the fact that all processors needing power inhibition in the N processors are subjected to power inhibition.
13. 13. The method according to any one of claims 1-10, wherein the power consumption suppressing process comprises: generating a frequency-reducing instruction aiming at a processor needing power suppression in the N processors; The frequency-reducing instruction is sent to a clock frequency adjusting unit corresponding to the processor needing power suppression; And performing frequency-reducing processing on the processor needing power suppression based on the frequency-reducing instruction through the clock frequency adjusting unit.
14. 14. A power consumption suppressing apparatus, belonging to the field of integrated circuit power consumption management, the apparatus comprising: The power supply unit comprises a determining module, a power supply unit and a power supply control module, wherein the determining module is used for determining respective load information of N processors in response to the occurrence of a power supply limiting risk of the power supply unit, the load information comprises load priority, priority information of a task is updated before the N processors execute the task, the updated priority information is sent to a load priority judging device through a hard wire, the respective load priorities of the N processors are ordered according to the priority information from low to high to determine the respective load priorities of the N processors, N is an integer greater than or equal to 2, the determining process of the occurrence of the power supply limiting risk of the power supply unit comprises the steps of acquiring a first power consumption value of each processor, determining a total second power consumption value of the N processors according to the first power consumption value of each processor, acquiring a third power consumption value corresponding to the maximum power supply capacity of the power supply unit, and determining the occurrence of the power supply limiting risk of the power supply unit in response to the second power consumption value greater than the third power consumption value; The power consumption suppression module is used for suppressing the power consumption of the N processors according to the load information; The device further comprises a step of responding to power supply limitation risk elimination of the power supply unit, a step of determining the load priority of the power-suppressed processor in the N processors, a step of sequencing the power-suppressed processor according to the load priority from high to low, a step of obtaining a power consumption recovery sequence, and a step of carrying out power consumption recovery on the power-suppressed processor according to the power consumption recovery sequence, wherein the power recovery process comprises the steps of generating an up-conversion instruction for the power-suppressed processor, sending the up-conversion instruction to a clock frequency adjusting unit corresponding to the power-suppressed processor, and a step of carrying out up-conversion processing on the power-suppressed processor through the clock frequency adjusting unit based on the up-conversion instruction.
15. 15. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the power consumption reduction method according to any one of claims 1-13 when executing the program.
16. 16. A computer-readable storage medium, on which a computer program is stored, characterized in that the program, when executed by a processor, implements the power consumption reduction method according to any one of claims 1-13.
17. 17. A computer program product comprising a computer program which, when executed by a processor, is implemented The power consumption suppressing method according to any one of claims 1 to 13.
18. 18. A chip, characterized in that the chip comprises a processing unit and an interface circuit, the processing unit obtaining program instructions through the interface circuit, the program instructions being executed by the processing unit, the processing unit being adapted to perform the steps of the power consumption reduction method according to any one of claims 1-13.

Description

Power consumption inhibition method and device, electronic equipment and chip Technical Field The present disclosure relates to the field of integrated circuit power consumption management, and in particular, to a power consumption suppression method, apparatus, electronic device, and chip. Background For complex System On Chip (SOC) chips, especially mobile SOC chips under the prior art, because various upper application layers are not required, such as artificial intelligence (ARTIFICIAL INTELLIGENCE, AI), large models, high resolution and high frame rate video and games, and the like, and the requirements of users On the experience of use are higher and higher, the performance requirements On the mobile SOC chips are further improved, but the high specification requirements On the power supply capability are caused by the improvement of the Chip performance, however, the power supply capability is limited by limited board area and thermal constraint, and the power supply specification cannot be improved without limitation, so how to fully release the performance of the chips under the limited power supply capability has become a problem to be solved. Disclosure of Invention The present disclosure provides a power consumption suppression method, apparatus, electronic device, computer-readable storage medium, computer program product, and chip. The technical scheme of the present disclosure is as follows: According to a first aspect of an embodiment of the present disclosure, there is provided a power consumption suppression method, including determining load information of each of N processors in response to occurrence of a power supply limitation risk of a power supply unit, where N is an integer greater than or equal to 2, and performing power consumption suppression on the N processors according to the load information. According to a second aspect of the embodiment of the present disclosure, there is provided a power consumption suppression device, including a determining module configured to determine load information of each of N processors in response to occurrence of a power supply limitation risk of a power supply unit, where N is an integer greater than or equal to 2, and a power consumption suppression module configured to perform power consumption suppression on the N processors according to the load information. According to a third aspect of embodiments of the present disclosure, there is provided an electronic device comprising a processor, a memory for storing instructions executable by the processor, wherein the processor is configured to execute the instructions to implement the power consumption reduction method as provided in the first aspect of the present disclosure. According to a fourth aspect of embodiments of the present disclosure, there is provided a computer-readable storage medium, which when executed by a processor of an electronic device, causes the electronic device to perform the power consumption reduction method as provided in the first aspect of the present disclosure. According to a fifth aspect of embodiments of the present disclosure, there is provided a computer program product comprising a computer program, characterized in that the computer program, when executed by a processor, implements the power consumption reduction method as provided in the first aspect of the present disclosure. According to a sixth aspect of embodiments of the present disclosure, there is provided a chip comprising a processing unit and an interface circuit, the processing unit obtaining program instructions through the interface circuit, the program instructions being executed by the processing unit, the processing unit being configured to perform the steps of the power consumption reduction method as provided in the first aspect. The technical scheme provided by the embodiment of the disclosure at least brings the following beneficial effects: According to the power consumption suppression method, in response to the power supply limited risk of the power supply unit, the load information of each of N processors is determined, N is an integer greater than or equal to 2, and the N processors are subjected to power consumption suppression according to the load information. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. Drawings The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure and do not constitute an undue limitation on the disclosure. Fig. 1 is a flow chart illustrating a power consumption suppression method according to an exemplary embodiment. Fig. 2 is a flow chart illustrating another power consumption reduction method according to an exemplary embodiment. Fig. 3 is