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CN-120561061-B - Mil-1394b interface transmission method and system based on FPGA

CN120561061BCN 120561061 BCN120561061 BCN 120561061BCN-120561061-B

Abstract

The invention discloses a method and a system for transmitting a Mil-1394b interface based on an FPGA, which adopt a GPU, a PCIE module, a Mil-1394b interface module, a link layer controller and a 1394 network which are sequentially connected, wherein the GPU converts high-speed parallel data into a serial data stream through the PCIE module, the protocol packaging is carried out through the Mil-1394b interface module, the link layer controller processes framing and verification of a data packet, and finally synchronous transmission among multiple nodes is realized through the 1394 network. The invention realizes a Mil-1394b interface which can be customized and developed according to different application requirements by utilizing the programmable characteristic of the FPGA and has high-speed data processing capability, high reliability and good compatibility.

Inventors

  • OuYang Xuhua

Assignees

  • 湖南泽天智航电子技术有限公司

Dates

Publication Date
20260505
Application Date
20250519

Claims (4)

  1. 1. The utility model provides a Mil-1394b interface transmission system based on FPGA, its characterized in that includes GPU (10), PCIE module (20), mil-1394b interface module (30), link layer controller (40) and 1394 network (50) that connect gradually, wherein, GPU (10) is through PCIE module (20) piece ‌ is with high-speed parallel data conversion serial data stream, after the protocol encapsulation is carried out through Mil-1394b interface module (30), by link layer controller (40) handles the framing and the check of data package, finally realizes the synchronous transmission between the multinode through 1394 network (50); The Mil-1394b interface module (30) comprises a ctrlreg unit, a MessageDownload unit, a MessageTxProcessTop unit and a TSB12LV32_IF unit which are sequentially connected; The Mil-1394b interface module (30) further comprises MessageRxProcessTop units and MessageUpload units, wherein the MessageRxProcessTop units are respectively connected with the MessageUpload units and the TSB12LV32_IF units; The Mil-1394b interface module (30) further comprises TimeCtrl units, wherein the TimeCtrl units are respectively connected with the MessageTxProcessTop units, the MessageRxProcessTop units and the TSB12LV32_IF units; The MessageRxProcessTop unit comprises a data packet analysis and filtering subunit, a data packet receiving FIFO subunit, a data packet receiving secondary FIFO subunit, a data packet receiving mark FIFO subunit and a data packet receiving mark secondary FIFO subunit, wherein the data packet analysis and filtering subunit is respectively connected with the data packet receiving FIFO subunit, the data packet receiving secondary FIFO subunit, the data packet receiving mark FIFO subunit and the data packet receiving mark secondary FIFO subunit; the MessageUpload unit comprises a data uploading subunit which is connected with the data packet receiving two-stage FIFO subunit; The TSB12LV32_IF unit comprises a microcomputer interface subunit and a DM interface subunit, and the link layer controller (40) is respectively connected with the microcomputer interface subunit and the DM interface subunit.
  2. 2. The FPGA-based Mil-1394b interface transmission system of claim 1, wherein the MessageDownload unit includes an interface conversion subunit, a transmit data cache RAM subunit, a transmit control stack dual port RAM subunit, and a packet update control subunit, and the transmit control stack dual port RAM subunit, the packet update control subunit, the interface conversion subunit, and the transmit data cache RAM subunit are sequentially connected.
  3. 3. The FPGA-based Mil-1394b interface transmission system of claim 1, wherein the MessageTxProcessTop units include a packet framing subunit and a packet buffering subunit coupled to the packet framing subunit.
  4. 4. An FPGA-based transmission method for a mill-1394 b interface, applied to an FPGA-based transmission system for a mill-1394 b interface according to any one of claims 1 to 3, characterized in that the FPGA-based transmission method for a mill-1394 b interface comprises the following steps: The 1394 data transmission processing flow is that a MessageDownload unit initiates DMA operation according to a control word in a control stack sent by a ctrlreg unit, a data packet is moved from a memory to a dual-port RAM in an FPGA, when the transmission offset time of the node arrives, a MessageTxProcessTop unit takes out the data packet from the dual-port RAM, adds frame tail information and sends the frame tail information to a TSB12LV32_IF unit, and the TSB12LV32_IF unit sends the data packet to a 1394 network; when the link layer controller is in the receiving mode, the TSB12LV32_IF unit stores the received data packet into MessageTxProcessTop units, messageTxProcessTop units transmit the data packet to MessageUpload units after completing the analysis and filtering of the data packet, and MessageUpload units transmit the data to a data uploading interface for DMA transmission.

Description

Mil-1394b interface transmission method and system based on FPGA Technical Field The invention relates to the technical field of interface control, and particularly discloses a method and a system for transmitting a Mil-1394b interface based on an FPGA. Background The requirements of reliability, certainty, safety and the like, which are emphasized in the field of aviation and on board, are that the development and application of the requirements of the SAE AS5643 interface are required to be in compliance with those proposed by the SAE AS1A3 Mil-1394b task group, which is called Mil-1394b. However, the existing Mil-1394b interface implementation has the problems of poor flexibility, slow processing speed, insufficient compatibility and expandability and the like. Therefore, the existing Mil-1394b interface implementation method has the defects of poor flexibility, slow processing speed, compatibility and expandability, and is a technical problem to be solved urgently. Disclosure of Invention The invention provides a method and a system for transmitting a Mil-1394b interface based on an FPGA, which aim to solve at least one of the defects existing in the prior Mil-1394b interface implementation method. The invention relates to a Mil-1394b interface transmission system based on an FPGA, which comprises a GPU, a PCIE module, a Mil-1394b interface module, a link layer controller and a 1394 network which are sequentially connected, wherein the GPU converts high-speed parallel data into serial data streams through the PCIE module, the protocol packaging is carried out through the Mil-1394b interface module, the link layer controller processes framing and verification of data packets, and finally synchronous transmission among multiple nodes is realized through the 1394 network. Further, the Mil-1394b interface module includes ctrlreg units, messageDownload units, messageTxProcessTop units, and TSB12LV32_IF units connected in order. Further, the Mil-1394b interface module further includes MessageRxProcessTop units and MessageUpload units, and MessageRxProcessTop units are connected to MessageUpload units and TSB12LV32_IF units, respectively. Further, the Mil-1394b interface module further includes TimeCtrl units, timeCtrl units respectively connected to MessageTxProcessTop units, messageRxProcessTop units, and TSB12LV32_IF units. Further, the MessageDownload unit includes an interface conversion subunit, a sending data buffer RAM subunit, a sending control stack dual-port RAM subunit and a data packet update control subunit, where the sending control stack dual-port RAM subunit, the data packet update control subunit, the interface conversion subunit and the sending data buffer RAM subunit are sequentially connected. Further, messageTxProcessTop units include a packet framing subunit and a packet buffering subunit connected to the packet framing subunit. Further, the MessageRxProcessTop unit includes a packet parsing and filtering subunit, a packet receiving FIFO subunit, a packet receiving second FIFO subunit, a packet receiving flag FIFO subunit, and a packet receiving flag second FIFO subunit, where the packet parsing and filtering subunit is connected to the packet receiving FIFO subunit, the packet receiving second FIFO subunit, the packet receiving flag FIFO subunit, and the packet receiving flag second FIFO subunit, respectively. Further, the MessageUpload unit includes a data upload subunit, which is connected to the data packet receiving two-stage FIFO subunit. Further, the TSB12LV32 IF unit includes a microcomputer interface subunit and a DM interface subunit, and the link layer controller is connected to the microcomputer interface subunit and the DM interface subunit, respectively. Another aspect of the present invention relates to a method for transmitting a Mil-1394b interface based on an FPGA, which is applied to the above-mentioned Mil-1394b interface transmission system based on an FPGA, and the method for transmitting a Mil-1394b interface based on an FPGA includes the following steps: The 1394 data transmission processing flow is that a MessageDownload unit initiates DMA operation according to a control word in a control stack sent by a ctrlreg unit, a data packet is moved from a memory to a dual-port RAM in an FPGA, when the transmission offset time of the node arrives, a MessageTxProcessTop unit takes out the data packet from the dual-port RAM, adds frame tail information and sends the frame tail information to a TSB12LV32_IF unit, and the TSB12LV32_IF unit sends the data packet to a 1394 network; when the link layer controller is in the receiving mode, the TSB12LV32_IF unit stores the received data packet into MessageTxProcessTop units, messageTxProcessTop units transmit the data packet to MessageUpload units after completing the analysis and filtering of the data packet, and MessageUpload units transmit the data to a data uploading interface for DMA transmission. The beneficial effects obta