CN-120728531-B - ESD electrostatic surge protection structure and method

CN120728531BCN 120728531 BCN120728531 BCN 120728531BCN-120728531-B

Abstract

The invention relates to a special protection technology for electronic elements, and provides an ESD electrostatic surge protection structure and method. The I/O pin is connected with the detection circuit and is used for inputting signals. The detection circuit is used for analyzing ESD electrostatic events or surge events and inputting a transient voltage suppressor and a discharging channel, wherein the transient voltage suppressor comprises a side path TSV path and a center TSV path. The detection circuit comprises a voltage sensor and a current sensor, wherein the voltage sensor is respectively connected with a first comparator and an amplitude detector, and the first comparator is used for monitoring the voltage slope of signals input by the I/O pins. The current sensor is connected to a second comparator for monitoring pulse energy and pulse duration of signals input by the plurality of I/O pins. Through multi-parameter dynamic analysis of voltage slope, pulse width, voltage peak value and pulse energy, accurate event identification and classified protection are realized.

Inventors

Chen Zhuxiong
CHEN HENGKAI
Cai Fangkai

Assignees

深圳市永裕泰电子有限公司

Dates

Publication Date: 20260508
Application Date: 20250621

Claims (10)

1. An ESD electrostatic surge protection structure comprises a plurality of I/O pins, a detection circuit, a transient voltage suppressor and a discharge channel, and is characterized in that, The I/O pin is connected with the detection circuit and is used for inputting signals; The detection circuit is used for analyzing ESD electrostatic events or surge events and inputting a transient voltage suppressor and a discharging channel, wherein the transient voltage suppressor comprises a side path TSV path and a center TSV path, Wherein, the The detection circuit comprises a voltage sensor and a current sensor, the voltage sensor is respectively connected with a first comparator and an amplitude detector, the first comparator is used for monitoring the voltage slope of the signal input by the I/O pin, The current sensor is connected with a second comparator for monitoring pulse energy and pulse duration of signals input by a plurality of I/O pins, The voltage slope, the pulse energy and the pulse duration are input into an event analysis unit, if the voltage slope exceeds a set threshold, the ESD event is judged, and the side path TSV path is conducted; if the pulse duration exceeds the set threshold, a surge event is determined, the central TSV path is turned on, wherein, If the pulse duration is less than or equal to 500ns, the ESD electrostatic event is directly judged to be conducted, the side path TSV path is conducted, if the voltage slope is more than 1V/ns, the pulse energy evaluation stage is conducted on the condition that the pulse width is more than 500ns, if the pulse energy exceeds 5mJ, the surge event is judged to be conducted, and if the pulse energy is less than 5mJ, the transient interference is judged to be conducted.
2. The ESD electrostatic surge protection structure of claim 1, wherein, If the voltage slope is less than or equal to 1V/ns, directly judging that the noise event is harmless; If the voltage slope is more than 1V/ns, if the pulse duration is less than or equal to 500ns, directly judging the ESD electrostatic event, and conducting the side path TSV path; if the voltage slope is more than 1V/ns and the pulse duration is more than 500ns, a pulse energy evaluation stage is carried out, the surge event is judged, the central TSV path is conducted at the moment, and if the pulse energy is lower than 5mJ, the transient interference is judged.
3. The ESD electrostatic surge protection structure of claim 1, wherein the lateral TSV path diameter is 20 μιη by 200 μιη, and the aspect ratio is 10:1, consisting of a polysilicon fill, a TiN barrier layer, and a SiO 2 insulating layer.
4. The ESD electrostatic surge protection structure of claim 1, wherein the central TSV path diameter is 80 μιη x 400 μιη with an aspect ratio of 5:1, consisting of copper fill, taN barrier layer, and air gap insulation layer.
5. The ESD electrostatic surge protection structure of claim 1, wherein the transient voltage suppressor further comprises a TVS diode connected to the side-by-side TSV path, the center TSV path, respectively, wherein the TVS diode comprises a p+ anode, an n+ cathode, and an epitaxial layer.
6. The ESD electrostatic surge protection structure of claim 5, wherein the TVS diode comprises a highly doped p++ substrate, a first epitaxial layer p++ isolation region is disposed on the p++ substrate, an n+ region is formed on a buried layer on the p++ isolation region, and an N-type epitaxial layer is formed by a second epitaxial process.
7. The ESD electrostatic surge protection structure of claim 6, wherein the p++ isolation region is used as a P-type region of the TVS diode and is connected to a highly doped p++ substrate, and an n+ region is formed on the surface of the P-type region, thereby forming a low breakdown voltage avalanche diode.
8. The ESD protection structure of claim 7 wherein the N-type epitaxial layer has highly doped P+ and N+ regions, wherein the P+/N-/N++ structure forms a PIN type low capacitance diode D2 and the N+/N-/P++ structure forms an NIP type low capacitance diode D1.
9. The ESD electrostatic surge protection structure of claim 1, wherein the detection circuit further comprises a temperature sensor and a thermal management unit, wherein the temperature sensor is coupled to the event analysis unit via the thermal management unit for overheat protection monitoring temperature.
10. An ESD electrostatic surge protection method comprising the ESD electrostatic surge protection structure of claim 1, further comprising the steps of: Step1, respectively detecting voltage and current in a circuit, and performing transient high-voltage protection and transient overcurrent protection; Step2, capturing voltage peaks of input signals in real time, and calculating voltage slopes of the input signals of a plurality of I/O pins; Step3, monitoring pulse width of signals input by a plurality of I/O pins, and calculating pulse energy; Step4, inputting the voltage slope, pulse energy and pulse duration into an event analysis unit to analyze a specific event, and controlling the conduction of a corresponding path by a path control unit; step5, the temperature sensor is connected with the event analysis unit through the thermal management unit and used for monitoring the temperature through overheat protection and performing predictive protection when the temperature exceeds a threshold value.

Description

ESD electrostatic surge protection structure and method Technical Field The present invention relates to protection technology for electronic components, and more particularly, to an ESD electrostatic surge protection structure and method. Background The ever shrinking technology nodes of Integrated Circuits (ICs) has led to increasingly miniaturized device dimensions, resulting in a chip with significantly increased susceptibility to transient voltage events such as electrostatic discharge (ESD, electrostatic Discharge) and surge (Surge). In practical applications, these high-energy, short-time transient disturbances may cause permanent damage to the internal circuitry of the chip, affecting system stability and reliability. Therefore, the introduction of efficient electrostatic surge protection structures into IC designs has become an indispensable key element. Conventional ESD protection schemes typically employ diode, MOS transistor, or Silicon Controlled Rectifier (SCR) structures as a bleed path, which is aimed at fast turn-on when an ESD event occurs, bleeding off the transient current to ground, and protecting the back-end circuit. However, such structures tend to have limited response speed and lack differential processing capability in the face of different types of transient events (e.g., ESD static or surge), which are prone to false triggering or insufficient response. In addition, conventional ESD protection devices may introduce large parasitic capacitances in the high frequency signal path, affecting signal integrity, especially in high speed I/O interfaces. On the other hand, the surge event has the characteristics of long duration and high energy, is commonly generated in the lightning stroke or power supply switching process, and the traditional ESD protection structure is difficult to bear the continuous energy impact, so that protection failure and even device burnout are caused. In view of this, there is a lack of a protection architecture in the prior art that can identify and dynamically respond to ESD and surge events, especially in high speed signal paths that achieve low parasitic capacitance, high response speed, and high energy carrying capacity. Disclosure of Invention In summary, the invention provides an ESD electrostatic surge protection structure and method, which aims to solve the problem of identifying and dynamically responding to ESD and surge events, and realize rapid response and accurate protection for different types of transient events. The technical scheme of the invention is realized as follows: An ESD electrostatic surge protection structure comprises a plurality of I/O pins, a detection circuit, a transient voltage suppressor and a discharge channel, and is characterized in that, The I/O pin is connected with the detection circuit and is used for inputting signals; The detection circuit is used for analyzing ESD electrostatic events or surge events and inputting a transient voltage suppressor and a discharging channel, wherein the transient voltage suppressor comprises a side path TSV path and a center TSV path, Wherein, the The detection circuit comprises a voltage sensor and a current sensor, the voltage sensor is respectively connected with a first comparator and an amplitude detector, the first comparator is used for monitoring the voltage slope of the signal input by the I/O pin, The current sensor is connected with a second comparator for monitoring pulse energy and pulse duration of signals input by a plurality of I/O pins, The voltage slope, the pulse energy and the pulse duration are input into an event analysis unit, if the voltage slope exceeds a set threshold, the ESD event is judged, and the side path TSV path is conducted; If the pulse duration exceeds the set threshold, a surge event is determined, and the central TSV path is turned on. It should be noted that the number of the substrates, If the voltage slope is less than or equal to 1V/ns, directly judging that the noise event is harmless; If the voltage slope is more than 1V/ns, if the pulse duration is less than or equal to 500ns, directly judging the ESD electrostatic event, and conducting the side path TSV path; if the voltage slope is more than 1V/ns and the pulse duration is more than 500ns, a pulse energy evaluation stage is carried out, the surge event is judged, the central TSV path is conducted at the moment, and if the pulse energy is lower than 5mJ, the transient interference is judged. The diameter of the path of the side-path TSV is 20 mu m multiplied by 200 mu m, the depth-to-width ratio is 10:1, and the path consists of a polysilicon filling layer, a TiN barrier layer and an SiO 2 insulating layer. The diameter of the central TSV path is 80 μm multiplied by 400 μm, the depth-to-width ratio is 5:1, and the central TSV path consists of copper filling, a TaN barrier layer and an air gap insulating layer. It should be noted that, the transient voltage suppressor further includes a T