CN-120745859-B - Quantum bit state readout circuit and quantum computing system

CN120745859BCN 120745859 BCN120745859 BCN 120745859BCN-120745859-B

Abstract

The application provides a qubit state reading circuit and a quantum computing system. The quantum bit state reading circuit comprises a low noise amplifier, a first local oscillator generator, a first mixer and a sampling clock generator, wherein the low noise amplifier is used for receiving and amplifying a multi-tone reflection signal of a quantum bit state reading resonant cavity, the first local oscillator generator is used for generating a first quadrature local oscillator signal required by first frequency down conversion of the multi-tone reflection signal, the first mixer is used for receiving the amplified multi-tone reflection signal output by the low noise amplifier and performing first frequency down conversion operation on the amplified multi-tone reflection signal under the control of the first quadrature local oscillator signal to generate a first frequency down conversion signal, the sampling clock generator is used for receiving a radio frequency local oscillator signal output by the first local oscillator generator and performing frequency division operation on the radio frequency local oscillator signal to generate a sampling clock signal, and the plurality of bit state detection links are used for finally acquiring state information of a plurality of quantum bits based on the first frequency down conversion signal and the sampling clock signal by adopting a multi-channel frequency division multiplexing technology.

Inventors

JIANG HANJUN
DENG NING
HUANG WENQIANG

Assignees

清华大学

Dates

Publication Date: 20260508
Application Date: 20250605

Claims (12)

1. A quantum bit state reading circuit is characterized by comprising a low noise amplifier, a first local oscillator generator, a first mixer, a sampling clock generator and a plurality of bit state detection links, wherein, The low noise amplifier is used for receiving a multi-tone reflection signal which reflects a multi-tone excitation signal through the quantum bit state readout resonant cavity and amplifying the multi-tone reflection signal; The first local oscillator generator is used for generating a first orthogonal local oscillator signal required by the first down-conversion of the multitone reflection signal; The first mixer is connected with the low noise amplifier and the first local oscillator generator and is used for receiving the amplified multi-tone reflected signal output by the low noise amplifier, and performing first down-conversion operation on the amplified multi-tone reflected signal under the control of the first orthogonal local oscillator signal to generate a first down-conversion signal; The sampling clock generator is connected with the first local oscillator generator and is used for receiving the radio frequency local oscillator signal output by the first local oscillator generator and carrying out frequency division operation on the radio frequency local oscillator signal to generate a sampling clock signal; The bit state detection links are connected with the first mixer and the sampling clock generator, and are used for finally obtaining state information of the quantum bits based on the first down-conversion signal and the sampling clock signal by adopting a multichannel frequency division multiplexing technology.
2. The qubit state readout circuit of claim 1 wherein the plurality of bit state detection links share a FIR filter and each of the bit state detection links comprises a second local oscillator generator, a second mixer, a low-pass power frequency conversion circuit, and a qubit state detector, wherein, The second local oscillator generator in each link is configured to generate a second quadrature local oscillator signal required for performing a second frequency down-conversion on the first down-converted signal; The second mixer in each link is connected with the first mixer and the second local oscillator generator of the corresponding link, and is used for performing a second down-conversion operation on the first down-conversion signal under the control of the second orthogonal local oscillator signal to generate a second down-conversion signal; The FIR filter is respectively connected with the sampling clock generator and a second mixer in each link and is used for carrying out narrow-band high-order filtering on the second down-conversion signal under the control of the sampling clock signal and outputting low-pass filtering signals corresponding to quantum bits of each link; the low-voltage power frequency conversion circuit in each link is used for receiving a low-pass filtering signal of a corresponding link output by the FIR filter and converting a voltage domain into a frequency domain; The qubit state detector in each link is used for receiving the frequency domain signal output by the low-voltage power-on frequency conversion circuit and detecting the qubit state of the link based on the frequency domain signal.
3. The qubit state readout circuit of claim 2 wherein the frequencies of the second quadrature local oscillator signals generated by the second local oscillator generators in different bit state detection links are different.
4. A qubit state readout circuit as claimed in claim 3, wherein the frequency of the second quadrature local oscillator signal for any one link is equal to the frequency difference between the link qubit state readout frequency and the frequency of the first quadrature local oscillator signal generated by the first local oscillator generator.
5. The qubit state readout circuit of any one of claim 2 to 4, wherein the sampling clock signal comprises a multi-phase sampling clock signal, the FIR filter comprises a plurality of tap circuits and a summer, each of the tap circuits comprising an input capacitance, a capacitive digital-to-analog converter, an output capacitance, and a transconductance amplifier, wherein, For any one of the links, the second down-conversion signal of the link is sequentially sampled onto the input capacitance of each tap circuit in time sequence through the multiphase sampling clock signal, the stored charges on the input capacitance finish multiplication operation of the corresponding tap coefficients through the capacitance digital-to-analog converter of the corresponding tap circuit, and the output charges of the capacitance digital-to-analog converter of each tap circuit are stored on the output capacitance and converted into the output current of the corresponding tap circuit of the link through the transconductance amplifier of the corresponding tap circuit; The summer is used for synthesizing and adding the output currents of all tap circuits corresponding to each link and outputting the synthesized current of each link, Wherein the low pass filtered signal output by the FIR filter corresponding to each link qubit comprises the combined current of each link output by the FIR filter.
6. The qubit state readout circuit of claim 5 wherein the tap circuit comprises a plurality of the input capacitors, a plurality of the output capacitors, and a plurality of the transconductance amplifiers corresponding to the plurality of bit state detection links, respectively, wherein a number of the input capacitors, the output capacitors, and the transconductance amplifiers is equal to a number of the plurality of bit state detection links, respectively, the capacitive digital-to-analog converter comprises a first capacitive digital-to-analog converter and a second capacitive digital-to-analog converter, wherein, Two ends of each input capacitor are connected with the second down-conversion signal of one link through a switch; the input ends of the first capacitance digital-to-analog converter and the second capacitance digital-to-analog converter are respectively and correspondingly connected with the two ends of each input capacitor; The output ends of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter are respectively and correspondingly connected with the two ends of each output capacitor; And two ends of each output capacitor are connected with two input ends of a corresponding transconductance amplifier, and the output end of each transconductance amplifier is used as the output end of the tap circuit corresponding to the link.
7. The qubit state readout circuit of claim 6 wherein each of the tap circuits further comprises a first driver, a second driver, a third driver, and a fourth driver, wherein, The two ends of each input capacitor are respectively connected with the input ends of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter through the first driver and the second driver, the input end of the first driver is in short circuit with the output end, and the input end of the second driver is in short circuit with the output end; The output ends of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter are respectively connected with two ends of each output capacitor through the third driver and the fourth driver, the input end of the third driver is in short circuit with the output end, and the input end of the fourth driver is in short circuit with the output end.
8. The qubit state readout circuit of any one of claims 1-4, wherein the low noise amplifier comprises a radio frequency inverter, a transformer, and a tunable capacitor, wherein, The radio frequency inverter is connected with the primary coil of the transformer, and the input end of the radio frequency inverter is connected with the multi-tone reflection signal; The secondary coil of the transformer is connected with the adjustable capacitor.
9. The qubit state readout circuit of any one of claims 2-4 wherein the low-pass power frequency conversion circuit comprises two low-pass voltage frequency converters for an I-path and a Q-path, each comprising a first differential inverter, a second differential inverter, and a current mirror, wherein, The positive phase input end of the first differential inverter is connected with the positive phase output end of the second differential inverter, the negative phase input end of the first differential inverter is connected with the negative phase output end of the second differential inverter, the positive phase output end of the first differential inverter is connected with the negative phase input end of the second differential inverter, the negative phase output end of the first differential inverter is connected with the positive phase input end of the second differential inverter, and the power supply ends of the first differential inverter and the second differential inverter are connected with power supply voltages; The input end of the current mirror is connected with the output end of the FIR filter, and the first output end and the second output end of the current mirror are respectively connected with the reference ground ends of the first differential inverter and the second differential inverter.
10. The qubit state readout circuit of claim 9 wherein the current mirror comprises a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, wherein, The grid electrodes of the first NMOS tube, the second NMOS tube and the third NMOS tube are connected together, the source electrodes of the first NMOS tube, the second NMOS tube and the third NMOS tube are grounded, and the drain electrodes of the first NMOS tube, the second NMOS tube and the third NMOS tube are respectively used as the input end, the first output end and the second output end of the current mirror.
11. A quantum computing system comprising an excitation signal generator, a qubit state readout resonant cavity, a qubit state readout circuit as claimed in any one of claims 1 to 10, a control terminal, wherein, The excitation signal generator is used for generating a multitone excitation signal under the control of the control terminal; The qubit state readout resonant cavity is used for reflecting the multitone excitation signal; The qubit state reading circuit is used for receiving the multitone reflection signals of the qubit state reading resonant cavity, reading state information of a plurality of qubits based on the multitone reflection signals and outputting the state information to the control terminal.
12. The quantum computing system of claim 11, further comprising a circulator having a first port, a second port, and a third port, wherein, The output end of the excitation signal generator is connected with the first port of the circulator, the qubit state reading resonant cavity is connected with the second port of the circulator, and the input end of the qubit state reading circuit is connected with the third port of the circulator.

Description

Quantum bit state readout circuit and quantum computing system Technical Field The application relates to the technical field of quantum computing and integrated circuits, in particular to a quantum bit state reading circuit and a quantum computing system. Background Qubits are the fundamental unit of quantum computation. The biggest challenges facing large-scale quantum computing are how to further increase the number of integrated qubits and reduce the volume of quantum computing platforms. At present, the qubit in the quantum computing platform needs to work in an ultralow temperature environment, and the state control and readout equipment of the qubit with larger volume needs to work at room temperature. Therefore, a cross-temperature-zone interconnect needs to be provided between the qubit and the qubit state control and readout device to achieve proper operation of both. Thus, the footprint of the quantum computing platform is further increased. Disclosure of Invention The present application is directed to a qubit state readout circuit and a quantum computing system, which can solve at least one technical problem mentioned in the above prior art. One aspect of the application provides a qubit state readout circuit. The qubit state readout circuit includes a low noise amplifier, a first local oscillator generator, a first mixer, a sampling clock generator, and a plurality of bit state detection links. The low noise amplifier is used for receiving a multi-tone reflection signal reflected by a multi-tone excitation signal through a quantum bit state readout resonant cavity and amplifying the multi-tone reflection signal, the first local oscillator generator is used for generating a first orthogonal local oscillator signal required by first frequency down conversion of the multi-tone reflection signal, the first mixer is connected with the low noise amplifier and the first local oscillator generator and is used for receiving the amplified multi-tone reflection signal output by the low noise amplifier and performing first frequency down conversion operation on the amplified multi-tone reflection signal under the control of the first orthogonal local oscillator signal to generate a first frequency down conversion signal, the sampling clock generator is connected with the first local oscillator generator and is used for receiving a radio frequency local oscillator signal output by the first local oscillator generator and performing frequency division operation on the radio frequency local oscillator signal to generate a sampling clock signal, and the plurality of bit state detection links are connected with the first mixer and the sampling clock generator and are used for acquiring multi-channel multi-frequency information through a multi-channel multiplexing technology based on the first frequency down conversion signal and the final sampling clock signal. The bit state detection links further comprise a second local oscillator generator, a second mixer, a low-voltage power-on frequency conversion circuit and a quantum bit state detector, wherein the second local oscillator generator in each link is used for generating a second quadrature local oscillator signal required for carrying out second frequency down conversion on the first down-conversion signal, the second mixer in each link is connected with the first mixer and the second local oscillator generator of the corresponding link and is used for carrying out second frequency down conversion operation on the first down-conversion signal under the control of the second quadrature local oscillator signal to generate a second down-conversion signal, the FIR filter is respectively connected with the sampling clock generator and the second mixer in each link and is used for carrying out narrow-band high-frequency filtering on the second down-conversion signal under the control of the sampling clock signal and outputting a low-pass filtered signal corresponding to each link bit, the low-pass frequency converter in each link is used for outputting a quantum-phase filter signal corresponding to the low-voltage domain of the low-voltage domain, and the low-voltage domain is used for detecting the quantum-state signal in the low-voltage domain. Further, the frequencies of the second quadrature local oscillator signals generated by the second local oscillator generators in different bit state detection links are different from each other. Further, the frequency of the second quadrature local oscillator signal of any link is equal to the frequency difference between the link qubit state readout frequency and the frequency of the first quadrature local oscillator signal generated by the first local oscillator generator. Further, the sampling clock signal comprises a multi-phase sampling clock signal, the FIR filter comprises a plurality of tap circuits and a summing device, each tap circuit comprises an input capacitor, a capacitor digital-to-analog converter, an