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CN-120779676-B - Method for realizing multi-chip high-density connection photoetching technology

CN120779676BCN 120779676 BCN120779676 BCN 120779676BCN-120779676-B

Abstract

The application discloses a method for realizing multi-chip high-density connection photoetching technology, a method for realizing multi-chip interconnection photoetching technology, a chip-level chip interconnection method, a method for manufacturing mask lines and photoetching equipment, wherein the method for realizing multi-chip high-density connection photoetching technology comprises the steps of selecting a first mask plate to be aligned with a first original graphic unit in a first M multiplied by N chip group through a second alignment mark for exposure, and transferring the first mask plate graph to an exposure area covering the first original graphic unit; and selecting other masks to repeatedly expose other corresponding graphic units of the first MXN chip set, and repeatedly executing the longitudinal movement or the transverse movement to complete the exposure of the corresponding areas of the corresponding graphic units in the other MXN chip sets. The scheme realizes multi-chip high-density interconnection.

Inventors

  • ZENG CHUANBIN
  • TIAN DAQING

Assignees

  • 北京中科彼岸集成电路科技有限公司

Dates

Publication Date
20260508
Application Date
20250620

Claims (20)

  1. 1. A method for implementing a multi-chip high density connection lithography technique for implementing an interconnect comprising mxn chips, comprising: Loading a substrate to be exposed with an original graphic unit to an objective table of a lithography device, and performing first alignment through a first alignment mark on the substrate; For a first MxN chip group on a substrate, selecting a first mask, aligning the first mask with a first original graphic unit in the first MxN chip group through a second alignment mark on the substrate, executing exposure, and transferring the first mask pattern to an exposure area covering the first original graphic unit; Repeatedly executing the alignment and exposure steps by longitudinally moving the substrate by M times the longitudinal dimension of the original graphic unit or transversely moving the substrate by N times the transverse dimension of the original graphic unit, and completing the exposure of the exposure area of the graphic unit corresponding to the first original graphic unit in other M multiplied by N chip sets on the substrate; Selecting other masks, repeatedly exposing corresponding graphic units except for a first original graphic unit of the first MxN chipset, and repeatedly performing longitudinal movement for M times of the longitudinal dimension of the original graphic unit or transverse movement for N times of the transverse dimension of the original graphic unit to complete exposure of corresponding areas of other corresponding graphic units in other MxN chipsets on the substrate; The method comprises the steps of forming an M X N chip group, wherein an overlapping area exists in the exposure area covering any original graphic unit and the exposure area of the original graphic unit adjacent to the same in any M X N chip group, and an interconnection line pattern which extends into the original graphic unit and is connected with the original graphic unit is not formed on the peripheral scribing channels of the M X N chip connected together in any M X N chip group; the overlapping area is an area generated by overlapping a first exposure area and a second exposure area of adjacent graphic units corresponding to adjacent exposure areas in the MxN chip set, wherein the first exposure area comprises a first line, a second line and a third line, the second exposure area comprises a fourth line, a fifth line and a sixth line, the first line is connected with the third line and the second line is connected with the third line, the fourth line is connected with the sixth line and the sixth line is connected with the fifth line; The first line is a line used for realizing connection between the first exposure area and the second exposure area in the first exposure area, the fourth line is a line used for realizing connection between the first exposure area and the second exposure area in the second exposure area, the second line is a line formed in an overlapping area of the first exposure area after the fourth line is swelled, the third line is a line used for strengthening connection between the first exposure area and the second exposure area in the first exposure area, the fifth line is a line formed in an overlapping area of the second exposure area after the first line is swelled, and the sixth line is a line used for strengthening connection between the first exposure area and the second exposure area in the second exposure area.
  2. 2. The method of claim 1, further comprising, prior to said performing the exposure: And biasing the substrate or a mask plate selected by executing the exposure by a preset offset distance.
  3. 3. The method according to claim 2, wherein, in the case that the second alignment mark is an alignment mark corresponding to an original graphic unit, the substrate or the mask selected to perform the exposure is preset with a corresponding offset distance, and the biasing the substrate or the mask selected to perform the exposure by the preset offset distance includes: When the mask plate selected by executing the exposure is loaded on a mask plate workbench, the mask plate selected by executing the exposure is offset by a preset offset distance, or And biasing the substrate by a preset offset distance.
  4. 4. The method according to claim 2, wherein the preset offset distance is 0 in the case where the second alignment mark is an alignment mark set for exposure to be performed.
  5. 5. The method according to claim 2, wherein the preset offset distance is 0 in the case where a relative positional relationship between a position of a mask pattern of a mask selected by performing the exposure in the mask and a position of a mask pattern of an original mask in the original mask is the same as a positional relationship of an exposure region to be formed by performing the exposure and the original pattern unit covered by the exposure region to be formed; Wherein the original mask is used for manufacturing the original graphic unit.
  6. 6. The method as recited in claim 1, further comprising: The expansion and contraction amount of the second line relative to the fourth line is larger than or equal to an alignment deviation limiting value between the first exposure area and the second exposure area, and the expansion and contraction amount of the fifth line relative to the first line is larger than or equal to the alignment deviation limiting value.
  7. 7. The method as recited in claim 1, further comprising: The first exposure area comprises a plurality of first lines, a plurality of second lines and a plurality of third lines, wherein a first interval is arranged between every two adjacent first lines, a second interval is arranged between every two adjacent second lines, and a third interval is arranged between every two adjacent third lines.
  8. 8. The method according to claim 7, wherein the first interval is an interval in a lateral direction, and the second interval and the third interval are intervals in a longitudinal direction when the first exposure region and the second exposure region overlap in a longitudinal direction.
  9. 9. The method according to claim 7, wherein the first interval is an interval in a longitudinal direction, and the second interval and the third interval are intervals in a lateral direction when the first exposure region and the second exposure region overlap in the lateral direction.
  10. 10. The method of any of claims 7-9, wherein the first spacing is greater than or equal to a minimum critical dimension of the lithographic apparatus.
  11. 11. The method of any of claims 7-9, wherein the second spacing is greater than or equal to a target value that is a maximum of a minimum critical dimension of the lithographic apparatus, an alignment deviation limit between the first exposure area and the second exposure area, when the dimension of the second line is greater than or equal to the dimension of the third line.
  12. 12. The method according to any one of claims 7 to 9, wherein the third interval is greater than or equal to a target value when the size of the second line is smaller than the size of the third line.
  13. 13. The method as recited in claim 1, further comprising: the second exposure area comprises a plurality of fourth lines, a plurality of fifth lines and a plurality of sixth lines, wherein a fourth interval is arranged between every two adjacent fourth lines, a fifth interval is arranged between every two adjacent fifth lines, and a sixth interval is arranged between every two adjacent sixth lines.
  14. 14. The method according to claim 13, wherein the fourth interval is an interval in a lateral direction, and the fifth interval and the sixth interval are intervals in a longitudinal direction when the first exposure region and the second exposure region overlap in the longitudinal direction.
  15. 15. The method according to claim 13, wherein the fourth interval is an interval in a longitudinal direction, and the fifth interval and the sixth interval are intervals in a lateral direction when the first exposure region and the second exposure region overlap in the lateral direction.
  16. 16. The method of any one of claims 13-15, wherein the fourth spacing is greater than or equal to a minimum critical dimension of the lithographic apparatus.
  17. 17. The method of any one of claims 13-15, wherein the fifth interval is greater than or equal to a target value when the size of the fifth line is greater than or equal to the size of the sixth line.
  18. 18. The method according to any one of claims 13 to 15, wherein the sixth interval is greater than or equal to a target value when the size of the fifth line is smaller than the size of the sixth line.
  19. 19. The method of claim 1, wherein the first exposure area comprises a plurality of first line sets, the second exposure area comprises a plurality of second line sets, each first line set comprises a plurality of first lines, a plurality of second lines and a plurality of third lines, each second line set comprises a plurality of fourth lines, a plurality of fifth lines and a plurality of sixth lines, each adjacent two first line sets have a first set interval therebetween, and each adjacent two second line sets have a second set interval therebetween.
  20. 20. The method of claim 19, wherein the first set of spaces and the second set of spaces are each a lateral space when the first exposure area and the second exposure area overlap in a longitudinal direction.

Description

Method for realizing multi-chip high-density connection photoetching technology Technical Field The application relates to the technical field of lithography machines, in particular to a method for realizing multi-chip high-density connection lithography, a method for realizing multi-chip interconnection lithography, a chip-level chip interconnection method, a method for manufacturing mask lines and lithography equipment. Background In modern semiconductor fabrication, photolithography is a critical step in the realization of high density integrated circuits. The photoetching process forms a required circuit structure by accurately transferring the pattern on the mask plate to photoresist on the surface of the silicon wafer. With the increasing integration of integrated circuits, the minimum size of the pattern (Critical Dimension, abbreviated as CD) is also becoming more and more critical. In lithography machine pattern exposure, the limit theoretical estimate of the minimum dimension of the pattern can be given by the Rayleigh rule for resolution, which is shown in equation (1): Formula (1) Wherein, the Is the wavelength of the light source of the lithographic apparatus used,Is the numerical aperture of the projection system of the lithography machine used for exposure,Is a regulator dependent on the lithographic process, also known as a Rayleigh Li Changshu,Is the minimum size of the pattern. As can be seen from the formula (1), there are three main ways to reduce the minimum size of the pattern, namely shortening the exposure wavelengthIncreasing the numerical apertureOr reduce. The difficulty of reducing the minimum size of the graph by the three approaches is excessive and the cost is excessive. In addition, as the device size is continuously reduced, the problem of leakage caused by quantum tunneling is more and more serious, and the feasibility of further reducing the minimum size of the graph is limited. Thus, simply relying on reducing the device critical dimensions to boost the number of transistors becomes no longer viable. To be able to accommodate more transistors, it becomes extremely important to manufacture larger chips. However, the maximum exposure field size of the conventional lithography machine is limited to about 26mm×33mm, and the requirement of manufacturing a larger-sized chip cannot be met. Although a large exposure field is realized in some liquid crystal panel fields, the line size obtained by the method is too wide, and the high-density integration requirement of an integrated circuit is difficult to meet. Therefore, how to realize high-density interconnection of multiple chips (e.g., multiple chips with sizes of about 26mm×33mm (e.g., 25mm×32 mm)) under the condition that the exposure field size is unchanged is a technical problem to be solved in the lithography technology. Disclosure of Invention The application provides a method for realizing multi-chip high-density connection photoetching technology, a method for realizing photoetching technology for multi-chip interconnection, a chip-level chip interconnection method, a method for manufacturing mask lines and photoetching equipment, and the method can realize multi-chip high-density interconnection under the condition that the size of an exposure field is unchanged, so that a large-size chip is formed, and photoetching technology support is provided for high-density interconnection integration of M multiplied by N multiple large chips. The specific scheme is as follows: In a first aspect, an embodiment of the present application provides a method for implementing a multi-chip high-density connection lithography technology, where the method is used for implementing interconnection including mxn chips, and the method includes: Loading a substrate to be exposed with an original graphic unit to an objective table of a lithography device, and performing first alignment through a first alignment mark on the substrate; For a first MxN chip group on a substrate, selecting a first mask, aligning the first mask with a first original graphic unit in the first MxN chip group through a second alignment mark on the substrate, executing exposure, and transferring the first mask pattern to an exposure area covering the first original graphic unit; Repeatedly executing the alignment and exposure steps by longitudinally moving the substrate by M times the longitudinal dimension of the original graphic unit or transversely moving the substrate by N times the transverse dimension of the original graphic unit, and completing the exposure of the exposure area of the graphic unit corresponding to the first original graphic unit in other M multiplied by N chip sets on the substrate; Selecting other masks, repeatedly exposing corresponding graphic units except for a first original graphic unit of the first MxN chipset, and repeatedly performing longitudinal movement for M times of the longitudinal dimension of the original graphic unit or transve