CN-120805832-B - Quick wiring method for self-adaptive standard frame adjustment and through hole optimization

CN120805832BCN 120805832 BCN120805832 BCN 120805832BCN-120805832-B

Abstract

The invention discloses a rapid wiring method for self-adaptive standard frame adjustment and through hole optimization, which comprises the steps of carrying out initialization division on a chip area to obtain an initialization area, carrying out congestion evaluation operation on the initialization area, judging whether congestion evaluation results reach a condition capable of being divided again, carrying out area classification on the division area if the congestion evaluation results reach a condition capable of being divided again, then carrying out dynamic adjustment division on the standard frame of the area again, carrying out wiring operation, adopting a weighted through hole influence evaluation model in the wiring process, and leading the wiring operation to preferentially select wiring paths for reducing through holes. The invention reduces DRC violations and obviously improves wiring efficiency based on a mechanism of dynamically adjusting the size of a standard frame by real-time congestion data, and more accurately measures the influence of the through holes on wiring quality by increasing the weight of the through holes through a weighted through hole influence evaluation model, and guides a wiring algorithm to preferentially select and reduce the wiring paths of the through holes so as to optimize DRC violations and the quantity of the through holes.

Inventors

HU JUN
YU WENXIN
WANG ZHILEI
ZHANG ZHIHAO
FU CHAOQI
Gong Mengshi

Assignees

西南科技大学

Dates

Publication Date: 20260508
Application Date: 20250701

Claims (6)

1. The rapid wiring method for self-adaptive standard frame adjustment and through hole optimization is characterized by comprising the following steps: S10, initializing and dividing a chip area to obtain an initialized area, wherein the initialized area is divided into standardized 8X 8 grid units, and each unit comprises a proper amount of pins and wires; S20, performing congestion evaluation operation on the initialized area, wherein the congestion evaluation operation comprises the steps of performing congestion evaluation on each unit after the initialized area is divided into 8 multiplied by 8 grid units, and calculating a congestion value of each unit to judge whether further subdivision is needed; S30, judging whether a congestion evaluation result reaches a condition capable of being divided again, if so, classifying the divided areas, and then dynamically adjusting and dividing the standard frames of the areas again; Setting a judging condition for whether secondary division is performed, judging the rewiring times of the area, and if the rewiring times reach a preset value, not allowing secondary division to be performed; S30, performing wiring operation, wherein a weighted through hole influence evaluation model is adopted in the wiring process, and the wiring operation is guided to preferentially select wiring paths for reducing the through holes; Traversing the connectable pins and dynamically selecting the next connection point based on a weighted via impact assessment model when wiring operation is performed; The weighted through hole influence evaluation model adopts a weighted cost model, minimizes Manhattan distance, penalizes excessive through hole use, and adaptively optimizes connection and resource allocation according to design requirements by controlling the weight of each factor; To evaluate each candidate pin, the cost of the potential path is calculated, cost function: Cost pin=Δx+Δy+Δz+α*via_count; Wherein Δx, Δy and Δz respectively represent a horizontal distance, a vertical distance and a vertical distance between the current pin and the candidate pin, via_count is the number of through holes estimated in the global wiring, α is an adjustable parameter, weight is given to the use of the through holes, and the number of the through holes is preferentially reduced.
2. The rapid routing method for adaptive standard frame adjustment and via optimization according to claim 1, wherein the congestion value is calculated according to the formula: Congestion=α×wlen+β×irs+γ×pins+δ×pins_area+ε×blks+ζ×blks_area+η×nets; Wherein wlen represents the global wiring line length of the area, irs represents the iroute number of the area, pins represents the pin number of the area, pins_area represents the area sum of pins of the area, blks represents the block number of the area, blks_area represents the area sum of blocks of the area, nets represents the different network segment numbers of the area, and alpha, beta, gamma, delta, epsilon, zeta and eta are weight parameters for adjusting the influence degree of each factor.
3. The adaptive standard frame adjustment and via optimization rapid routing method of claim 1, wherein each region is divided into high congestion, medium congestion and low congestion regions after congestion assessment, and the standard frame size is matched for each type of region.
4. A rapid routing method for adaptive standard frame adjustment and via optimization according to claim 3, wherein the high congestion area remains at 8 x 8, providing sufficient computing resources to optimize routing; the medium congestion area is reduced to 4 multiplied by 4, so that the wiring quality and the efficiency are both considered; the low congestion area is further reduced to 2 x 2, increasing the wiring speed and reducing the computation time.
5. The adaptive standard frame adjustment and via optimization rapid routing method of claim 4, wherein after region classification, a secondary partitioning is performed on regions marked as low congestion to further refine the routing resource allocation.
6. The method for rapid routing for adaptive standard frame adjustment and via optimization according to claim 4, wherein in the secondary division stage, small grids are subdivided into areas with low congestion, and the number of rewiring is determined, and if the number of rewiring of an area exceeds a preset upper limit, the area is not allowed to be divided again.

Description

Quick wiring method for self-adaptive standard frame adjustment and through hole optimization Technical Field The invention belongs to the technical field of circuit wiring, and particularly relates to a rapid wiring method for self-adaptive standard frame adjustment and through hole optimization. Background In the field of integrated circuit detailed wiring, the design of a wiring frame and the selection of a pin sequence still lack sufficient attention, and currently, a fixed frame scheme is mostly adopted. And carrying out a plurality of detailed wiring iterations according to the track distribution result. In each iteration, the design is divided into 7×7 non-overlapping tiles that are aligned with Grid cells, and one detailed wiring work unit (worker) is created for each tile. Each detailed routing unit work first initializes its own data structure (unit work database) from the global database, and then performs routing and design rule checking (Design Rule Check) without modifying the global database. Finally, each work cell commits the changes by writing back to the global database. In alternate iterations, the 7 x 7 patch partitions are adjusted by offsets of 0 and-4 to optimize routing at the patch boundaries. In building a detailed wiring work cell, each tile has three bounding boxes, a standard bounding box, a Design Rule Check (DRC) bounding box, and an extended bounding box. In the database of the detailing work units, all objects within the expanded bounding box are built locally. But only objects that lie or are within the standard bounding box may be modified while other objects are fixed. The fixed object is used for cost calculation and design rule checking. Most of the existing wiring frames distribute wiring space based on standard frames with single and fixed sizes, and the fixed frame scheme in the traditional algorithm is suitable for the wiring environment with uniform density. However, the limitations of the fixed frame in modern designs are emerging, and it is difficult to meet the need for fine wiring, especially in high density, locally congested chip areas. In the wiring of the fixed frame, since the size of the frame has a significant influence on the search space of the algorithm a, the large frame can provide a larger search space, which is beneficial to the optimization of complex paths, but increases the calculation overhead and the search time of the algorithm. In a low-congestion area, a smaller framework can effectively reduce search space and calculation complexity and accelerate wiring speed. However, current fixed frame designs cannot accommodate the differential requirements of local areas, where large frames in high density areas increase search space, resulting in excessive consumption of computing resources, and where too small frames may result in a lack of flexibility in path selection, which makes balancing efficiency and quality difficult. In addition, the pin selection strategy is still based on conventional shortest path algorithms, and is generally optimized based on Manhattan distance. However, this single consideration fails to sufficiently pay attention to the influence of the number of through holes on the overall wiring quality. In multilayer wiring designs, the number of vias directly affects the delay of signal transmission and process complexity, and especially as design nodes tend to be smaller in process level, via management becomes an important factor affecting wiring performance. Although research has been attempted to introduce a via penalty term in path selection, the overall approach is biased towards post-processing, failing to take full consideration in advance, increasing routing resource waste. Disclosure of Invention In order to solve the problems, the invention provides a self-adaptive standard frame adjustment and through hole optimization rapid wiring method, which is based on a mechanism for dynamically adjusting the size of a standard frame based on real-time congestion data, dynamically adjusts the size of the standard frame according to the pin density, the wire density and the metal shape density in an area, reduces DRC violations, remarkably improves wiring efficiency, and more accurately measures the influence of the through holes on wiring quality by increasing the weight used by the through holes through a weighted through hole influence evaluation model, and guides a wiring algorithm to preferentially select wiring paths for reducing the through holes so as to optimize DRC violations and the number of the through holes. In order to achieve the purpose, the technical scheme adopted by the invention is that the rapid wiring method for adjusting the self-adaptive standard frame and optimizing the through holes comprises the following steps: s10, carrying out initialization division on a chip area to obtain an initialization area; S20, performing congestion evaluation operation on the initialized region; S30, judging whether a