CN-120811375-B - Data acquisition method and data acquisition card

CN120811375BCN 120811375 BCN120811375 BCN 120811375BCN-120811375-B

Abstract

The embodiment of the invention discloses a data acquisition method and a data acquisition card. The data acquisition method is applied to a data acquisition card, and comprises a comparator, a delay module, a fan-out module, a field programmable gate array, an analog-to-digital conversion module and a data acquisition method, wherein the delay module is in communication connection with the comparator, the fan-out module is in communication connection with the delay module and is used for dividing a trigger signal output by the delay module by N, N is an integer larger than 1, the field programmable gate array is in communication connection with the fan-out module and comprises a clock unit, the analog-to-digital conversion module is in communication connection with the field programmable gate array, the data acquisition method comprises the steps of receiving an instruction, controlling all clock signals of the clock unit to have the same frequency according to the instruction, dividing the phase by N equally, receiving the trigger signal transmitted by the fan-out module and a digital signal transmitted by the analog-to-digital conversion module, processing the trigger signal based on the clock signal, and reordering the digital signals according to the processed trigger signal. The technical scheme provided by the embodiment of the invention can improve the data acquisition precision.

Inventors

LI GUIYANG
ZHOU LEI
JI ERYOU
WU DANYU

Assignees

迅芯微电子(苏州)股份有限公司

Dates

Publication Date: 20260508
Application Date: 20250630

Claims (9)

1. The data acquisition method is characterized in that the data acquisition method is applied to a data acquisition card, and the data acquisition card comprises: The comparator is used for receiving a trigger signal and a trigger threshold value, and outputting the trigger signal when the amplitude of the trigger signal is greater than or equal to the trigger threshold value; The delay module is in communication connection with the comparator and is used for delaying the trigger signal output by the comparator and outputting the delayed trigger signal; the fan-out module is in communication connection with the delay module and is used for dividing the trigger signals output by the delay module into N paths of trigger signals and outputting all paths of trigger signals, wherein N is an integer greater than 1; A field programmable gate array in communication with the fan-out module, the field programmable gate array comprising a clock unit; the analog-to-digital conversion module is in communication connection with the field programmable gate array and is used for receiving analog signals, converting the analog signals into digital signals and outputting the digital signals to the field programmable gate array; The data acquisition method comprises the following steps: Receiving an instruction; according to the instruction, controlling each clock signal frequency of the clock unit to be identical and dividing the phase N equally; receiving a trigger signal transmitted by the fan-out module and a digital signal transmitted by the analog-to-digital conversion module, processing the trigger signal based on the clock signal, and reordering the digital signal according to the processed trigger signal; the processing the trigger signal based on the clock signal and reordering the digital signal according to the processed trigger signal includes: Performing serial-parallel conversion on the trigger signals based on the clock signals, splicing trigger data of the serial-parallel converted trigger signals, and extracting target signals from the spliced trigger data; reordering the digital signals according to the target signal; The step of performing serial-parallel conversion on the trigger signal based on the clock signal, and performing splicing on trigger data of the serial-parallel converted trigger signal, and extracting a target signal from the spliced trigger data comprises the following steps: n clock signals are equally divided into N phases, N paths of trigger signals are respectively converted into low-frequency and multi-bit wide signals based on N clock signals with the same frequency and the equally divided N phases in a serial-parallel mode, the trigger signals after serial-parallel conversion are spliced into trigger data, and the positions of the signals are determined according to the spliced trigger data to extract target signals.
2. The data acquisition method according to claim 1, wherein the controlling the clock units before the clock signals are identical in frequency and equally divided by the phase N comprises: And carrying out delay calibration on the delay module and the field programmable gate array.
3. The method of claim 2, wherein before performing delay calibration on the delay module and the field programmable gate array, the method comprises: And controlling the clock signals of the clock unit to be in the same frequency and phase.
4. A data acquisition card, comprising: The comparator is used for receiving a trigger signal and a trigger threshold value, and outputting the trigger signal when the amplitude of the trigger signal is greater than or equal to the trigger threshold value; The delay module is in communication connection with the comparator and is used for delaying the trigger signal output by the comparator and outputting the delayed trigger signal; the fan-out module is in communication connection with the delay module and is used for dividing the trigger signals output by the delay module into N paths of trigger signals and outputting all paths of trigger signals, wherein N is an integer greater than 1; The field programmable gate array is in communication connection with the fan-out module, and comprises a clock unit, wherein each clock signal of the clock unit has the same frequency and is equally divided into phases N; the analog-to-digital conversion module is in communication connection with the field programmable gate array and is used for receiving analog signals, converting the analog signals into digital signals and outputting the digital signals to the field programmable gate array, and the field programmable gate array is also used for reordering the digital signals according to the processed trigger signals; The field programmable gate array comprises a trigger module and a data sorting module, wherein the trigger module is in communication connection with the fan-out module and the data sorting module, and the data sorting module is in communication connection with the analog-to-digital conversion module; The clock unit is used for transmitting clock signals with the same frequency phase N to the serial-parallel conversion unit, the serial-parallel conversion unit is used for carrying out serial-parallel conversion on the trigger signals transmitted by the fan-out module according to the clock signals, the trigger data processing unit is used for splicing trigger data on the trigger signals after serial-parallel conversion, the target signals are extracted from the spliced trigger data, and the data sequencing module is used for re-sequencing the digital signals according to the target signals; The clock unit is used for respectively transmitting N clock signals with N identical frequency phases and N equal division to the corresponding N serial-parallel conversion units, and the N serial-parallel conversion units corresponding to the same clock unit are used for sequentially carrying out serial-parallel conversion on N paths of trigger signals transmitted by the fan-out module according to the clock signals and the equal interval phases.
5. The data acquisition card of claim 4, wherein the delay modules and the fan-out modules are at least two, the delay modules and the fan-out modules are in one-to-one correspondence, each delay module is in communication connection with the corresponding fan-out module, and each delay module is used for sequentially delaying the trigger signal output by the comparator.
6. The data acquisition card of claim 4, wherein the field programmable gate array comprises a trigger module and a data sorting module, the trigger module is in communication connection with the fan-out module and the data sorting module, the data sorting module is in communication connection with the analog-to-digital conversion module, the trigger module is used for receiving each path of trigger signal output by the fan-out module and processing the trigger signal based on the clock signal, and the data sorting module is used for re-sorting the digital signals transmitted by the analog-to-digital conversion module according to the processed trigger signal.
7. The data acquisition card according to claim 6, wherein the trigger module comprises the clock unit, a serial-to-parallel conversion unit and a trigger data processing unit, the clock unit is in communication connection with the serial-to-parallel conversion unit, the fan-out module, the serial-to-parallel conversion unit and the trigger data processing unit are in communication connection in sequence, the clock unit is used for transmitting clock signals equally divided by a same frequency phase N to the serial-to-parallel conversion unit, the serial-to-parallel conversion unit is used for carrying out serial-to-parallel conversion on trigger signals transmitted by the fan-out module according to the clock signals, the trigger data processing unit is used for splicing trigger data of the serial-to-parallel converted trigger signals, the target signals are extracted from the spliced trigger data, and the data sequencing module is used for reordering the digital signals according to the target signals.
8. The data acquisition card of claim 7, wherein the delay module, the fan-out module, the clock units and the trigger data processing units are N and are in one-to-one correspondence, the serial-to-parallel conversion units are n×n in number, each fan-out module and each clock unit corresponds to N serial-to-parallel conversion units, N is an integer greater than 1, N is equal to or different from N, the clock units are used for respectively transmitting N clock signals with N identical frequency phases being N equally divided to the corresponding N serial-to-parallel conversion units, and N serial-to-parallel conversion units corresponding to the same clock unit are used for sequentially performing serial-to-parallel conversion on N trigger signals transmitted by the fan-out module according to the clock signals at equal interval phases.
9. The data acquisition card of claim 4 further comprising an analog front end module in communication with the analog to digital conversion module, the analog front end module configured to receive analog signals and process the analog signals, and to transmit the processed analog signals to the analog to digital conversion module.

Description

Data acquisition method and data acquisition card Technical Field The embodiment of the invention relates to a data acquisition technology, in particular to a data acquisition method and a data acquisition card. Background In a scenario where data is to be processed or analyzed, data is collected. At present, the existing data acquisition method has the problem of low data acquisition precision. Disclosure of Invention The embodiment of the invention provides a data acquisition method and a data acquisition card so as to improve data acquisition accuracy. In a first aspect, an embodiment of the present invention provides a data acquisition method, where the data acquisition method is applied to a data acquisition card, and the data acquisition card includes: The comparator is used for receiving a trigger signal and a trigger threshold value, and outputting the trigger signal when the amplitude of the trigger signal is greater than or equal to the trigger threshold value; The delay module is in communication connection with the comparator and is used for delaying the trigger signal output by the comparator and outputting the delayed trigger signal; the fan-out module is in communication connection with the delay module and is used for dividing the trigger signals output by the delay module into N paths of trigger signals and outputting all paths of trigger signals, wherein N is an integer greater than 1; A field programmable gate array in communication with the fan-out module, the field programmable gate array comprising a clock unit; the analog-to-digital conversion module is in communication connection with the field programmable gate array and is used for receiving analog signals, converting the analog signals into digital signals and outputting the digital signals to the field programmable gate array; The data acquisition method comprises the following steps: Receiving an instruction; according to the instruction, controlling each clock signal frequency of the clock unit to be identical and dividing the phase N equally; And receiving the trigger signal transmitted by the fan-out module and the digital signal transmitted by the analog-to-digital conversion module, processing the trigger signal based on the clock signal, and reordering the digital signal according to the processed trigger signal. Optionally, before the controlling the clock signals of the clock unit with the same frequency and the equal phase N, the method includes: And carrying out delay calibration on the delay module and the field programmable gate array. Optionally, before the delay module and the field programmable gate array perform delay calibration, the method includes: And controlling the clock signals of the clock unit to be in the same frequency and phase. Optionally, the processing the trigger signal based on the clock signal and reordering the digital signals according to the processed trigger signal includes: Performing serial-parallel conversion on the trigger signals based on the clock signals, splicing trigger data of the serial-parallel converted trigger signals, and extracting target signals from the spliced trigger data; and reordering the digital signals according to the target signal. In a second aspect, an embodiment of the present invention provides a data acquisition card, including: The comparator is used for receiving a trigger signal and a trigger threshold value, and outputting the trigger signal when the amplitude of the trigger signal is greater than or equal to the trigger threshold value; The delay module is in communication connection with the comparator and is used for delaying the trigger signal output by the comparator and outputting the delayed trigger signal; the fan-out module is in communication connection with the delay module and is used for dividing the trigger signals output by the delay module into N paths of trigger signals and outputting all paths of trigger signals, wherein N is an integer greater than 1; The field programmable gate array is in communication connection with the fan-out module, and comprises a clock unit, wherein each clock signal of the clock unit has the same frequency and is equally divided into phases N; The analog-to-digital conversion module is in communication connection with the field programmable gate array and is used for receiving analog signals, converting the analog signals into digital signals and outputting the digital signals to the field programmable gate array, and the field programmable gate array is also used for reordering the digital signals according to the processed trigger signals. Optionally, the number of delay modules and the number of fan-out modules are at least two, the delay modules and the fan-out modules are in one-to-one correspondence, each delay module is in communication connection with the corresponding fan-out module, and each delay module is used for sequentially delaying the trigger signal output by the comparator. Optionally, the fie