CN-120893370-B - Simulation integration method and system of FPGA communication module

CN120893370BCN 120893370 BCN120893370 BCN 120893370BCN-120893370-B

Abstract

The invention provides a simulation integration method and system of an FPGA communication module, comprising the following steps of S1, S2, performing interface adaptation on a system bus access part accessing the FPGA communication module in a full-digital simulation system based on FPGA simulation module codes, S3, introducing another module which is completely the same as the FPGA communication module as a symmetrical module, and performing cross connection of a transceiving interface of the symmetrical module and the FPGA communication module, and S4, performing interface adaptation on a communication data receiving side of the symmetrical module according to a bus access mode in the full-digital simulation system. The FPGA module simulation is based on the source codes of the FPGA, so that the accuracy of the FPGA simulation behavior is improved.

Inventors

WANG YAOLIN
QIN WEI

Assignees

上海创景信息科技股份有限公司

Dates

Publication Date: 20260508
Application Date: 20250928

Claims (4)

1. The simulation integration method of the FPGA communication module is characterized by comprising the following steps of: S1, converting IP source codes of an FPGA communication module into FPGA simulation module codes of C++ language; Step S2, based on FPGA simulation module codes, performing interface adaptation on a system bus access part accessing an FPGA communication module in the all-digital simulation system; s3, introducing another module which is completely the same as the FPGA communication module as a symmetrical module, and carrying out cross connection of a receiving-transmitting interface of the symmetrical module and the FPGA communication module; s4, on a communication data receiving side of the symmetrical module, performing interface adaptation according to a bus access mode in the all-digital simulation system; The step S1 specifically comprises the following steps: S1.1, analyzing and verifying IP source codes of FPGA communication modules, extracting top-layer module interfaces from the IP source codes, wherein the top-layer module interfaces comprise clock and reset interfaces, system bus interfaces and communication bus interfaces; s1.2, based on the extracted top-layer module interface, converting IP source codes of an FPGA communication module into FPGA simulation module codes of C++ language, and providing FPGA simulation model classes containing all top-layer module interfaces in the FPGA simulation module codes of C++ language; s1.3, compiling FPGA simulation module codes of C++ language to generate a static link library of an FPGA communication module; the step S2 specifically includes the following steps: step S2.1, instantiating the FPGA communication module in the step S1.2; Step S2.2, defining data of bus interface signals aiming at the instantiated FPGA communication module, wherein the data of the bus interface signals comprise a clock and reset interface, a system bus interface and a communication bus interface in the step S1.1; S2.3, according to the operation instruction of the bus interface type of the all-digital simulation system, the data of the operation bus interface signals are changed, the read-write operation of the bus is simulated, and the interface adaptation of the system bus access part is completed; the step S3 specifically includes the following steps: Step S3.1, instantiating a module which is completely the same as the FPGA communication module in the step S2.1 and is used as a symmetrical module; Step S3.2, connecting the data transmitting end of the FPGA communication module in the step S2.1 with the data receiving end of the symmetrical module in the step S3.1, and simultaneously connecting the data receiving end of the FPGA communication module in the step S2.1 with the data transmitting end of the symmetrical module in the step S3.1 to realize cross connection of the receiving interface and the transmitting interface; the step S4 specifically includes the following steps: Step S4.1, after the bus writing operation is completed for the FPGA communication module in step S2.3, the clock is delayed for a preset time, then the read operation is executed for the data bus interface part of the symmetrical module in step S3.1 according to the operation description of the bus interface type of the all-digital simulation system, the operation data corresponding to the bus writing operation is obtained through the read operation, and the interface adaptation related to the receiving side writing operation of the symmetrical module is completed; And step S4.2, after the write operation is performed on the data bus interface part of the symmetrical module in the step S3.1 according to the operation description of the bus interface type of the all-digital simulation system, the clock is delayed for a preset time, and then the read operation is performed on the FPGA communication module in the step S2.1 according to the bus access mode of the step S2.3, so that the interface adaptation of the write operation of the symmetrical module receiving side corresponding to the read operation of the FPGA module is completed.
2. The simulation integrated system of the FPGA communication module is characterized by comprising the following modules: the module M1 is used for converting the IP source code of the FPGA communication module into an FPGA simulation module code of C++ language; The module M2 is used for performing interface adaptation on a system bus access part accessing the FPGA communication module in the all-digital simulation system based on the FPGA simulation module code; The module M3 is used for introducing another module which is completely the same as the FPGA communication module as a symmetrical module, and carrying out cross connection of a receiving-transmitting interface of the symmetrical module and the FPGA communication module; the module M4 is used for performing interface adaptation on the communication data receiving side of the symmetrical module according to a bus access mode in the all-digital simulation system; The module M1 specifically includes the following modules: analyzing and verifying IP source codes of the FPGA communication module, extracting a top-layer module interface from the IP source codes, wherein the top-layer module interface comprises a clock and reset interface, a system bus interface and a communication bus interface; The module M1.2 is used for converting IP source codes of the FPGA communication module into FPGA simulation module codes of C++ language based on the extracted top-layer module interfaces, and providing FPGA simulation model classes containing all top-layer module interfaces in the FPGA simulation module codes of C++ language; compiling FPGA simulation module codes of C++ language to generate a static link library of the FPGA communication module; the module M2 specifically includes the following modules: the module M2.1 instantiates the FPGA communication module in the module M1.2; The module M2.2 is used for defining data of bus interface signals aiming at the instantiated FPGA communication module, wherein the data of the bus interface signals comprise a clock and reset interface, a system bus interface and a communication bus interface in the module M1.1; the module M2.3 is used for changing the data of the operation bus interface signals according to the operation instruction of the bus interface type of the all-digital simulation system, simulating the read-write operation of the bus and completing the interface adaptation of the system bus access part; the module M3 specifically includes the following modules: the module M3.1 is used for instantiating a module which is completely the same as the FPGA communication module in the module M2.1 and is used as a symmetrical module; The module M3.2 is used for connecting the data transmitting end of the FPGA communication module in the module M2.1 with the data receiving end of the symmetrical module in the module M3.1, and simultaneously connecting the data receiving end of the FPGA communication module in the module M2.1 with the data transmitting end of the symmetrical module in the module M3.1 to realize the cross connection of the receiving interface and the transmitting interface; The module M4 specifically includes the following modules: After the bus writing operation is completed for the FPGA communication module in the module M2.3, the clock is delayed for a preset time, then the read operation is executed for the data bus interface part of the symmetrical module in the module M3.1 according to the operation description of the bus interface type of the all-digital simulation system, the operation data corresponding to the bus writing operation is obtained through the read operation, and the interface adaptation related to the receiving side writing operation of the symmetrical module is completed; And the module M4.2 performs a read operation on the FPGA communication module in the module M2.1 according to a bus access mode of the module M2.3 after performing a write operation on the data bus interface part of the symmetrical module in the module M3.1 according to the operation description of the bus interface type of the all-digital simulation system, and completes interface adaptation of the symmetrical module receiving side write operation corresponding to the read operation of the FPGA module.
3. The simulation integrated system of the FPGA communication module is characterized by comprising a first simulation bus interface module, a first simulation FPGA communication module, a second simulation FPGA communication module and a second simulation bus interface module; The first simulation bus interface module and the first simulation FPGA communication module are used for data transmission, the first simulation FPGA communication module and the second simulation FPGA communication module are used for data transmission, and the second simulation FPGA communication module and the second simulation bus interface module are used for data transmission; The first simulation FPGA communication module converts IP source codes of the first simulation FPGA communication module into FPGA simulation module codes of C++ language, and the first simulation bus interface module performs interface adaptation based on the FPGA simulation module codes; The second simulation FPGA communication module is the same as the first simulation FPGA communication module, and is used as a symmetrical module of the first simulation FPGA communication module; the receiving and transmitting interface of the second simulation bus interface module is cross-connected with the receiving and transmitting interface of the first simulation bus interface module, so that interface adaptation of the second simulation bus interface module is realized; Analyzing and verifying the IP source code of the FPGA communication module, extracting a top-layer module interface from the IP source code, wherein the top-layer module interface comprises a clock and reset interface, a system bus interface and a communication bus interface; Based on the extracted top-layer module interfaces, converting IP source codes of the FPGA communication module into FPGA simulation module codes of C++ language, and providing FPGA simulation model classes containing all top-layer module interfaces in the FPGA simulation module codes of C++ language; compiling the FPGA simulation module codes of the C++ language to generate a static link library of the FPGA communication module; Instantiating an FPGA communication module; Defining data of bus interface signals aiming at the instantiated FPGA communication module, wherein the data of the bus interface signals comprise a clock and reset interface, a system bus interface and a communication bus interface; According to the operation instruction of the bus interface type of the all-digital simulation system, the data of the operation bus interface signals are changed, the read-write operation of the bus is simulated, and the interface adaptation of the system bus access part is completed; Instantiating a module which is completely the same as the FPGA communication module and is used as a symmetrical module; Connecting a data transmitting end of the FPGA communication module with a data receiving end of the symmetrical module, and simultaneously connecting the data receiving end of the FPGA communication module with the data transmitting end of the symmetrical module to realize cross connection of the receiving and transmitting interfaces of the two; After bus writing operation is completed on the FPGA communication module, a clock is delayed for a preset time, and then a data bus interface part of the symmetrical module executes reading operation according to the operation description of the bus interface type of the all-digital simulation system, operation data corresponding to the bus writing operation is obtained through the reading operation, and interface adaptation related to the receiving side writing operation of the symmetrical module is completed; After the write operation is executed on the data bus interface part of the symmetrical module according to the operation description of the bus interface type of the all-digital simulation system, the clock is delayed for a preset time, then the read operation is executed on the FPGA communication module according to the bus access mode, and the interface adaptation of the write operation of the symmetrical module receiving side corresponding to the read operation of the FPGA module is completed.
4. The system of claim 3, wherein the first emulation bus interface module comprises an emulation CPU access interface, a first clock and reset interface, and a first system bus interface; The first simulation FPGA communication module comprises a second clock and reset interface, a second system bus interface and a first communication bus interface; The second simulation FPGA communication module comprises a third clock and reset interface, a third system bus interface and a second communication bus interface; the second simulation bus interface module comprises a fourth clock and reset interface, a fourth system bus interface and a UI interaction interface; The simulation CPU access interface is connected with the simulation CPU, the first clock and reset interface is connected with the second clock and reset interface, and the first system bus interface is connected with the second system bus interface; the first communication bus interface is connected with the second communication bus interface; The third clock and reset interface is connected with the fourth clock and reset interface, the third system bus interface is connected with the fourth system bus interface, and the UI interaction interface is connected with the UI interaction module.

Description

Simulation integration method and system of FPGA communication module Technical Field The invention relates to the technical field of all-digital simulation, in particular to a simulation integration method and system of an FPGA communication module, and especially relates to a simulation integration method and system of an FPGA communication module used in an all-digital simulation system. Background An FPGA is a programmable logic device that is widely used in a variety of scenarios requiring high performance, low latency, and flexible hardware design. In recent years, the method has been widely applied in the fields of aerospace, national defense and military industry, industry and communication. Because the application of the FPGA on military weapons such as national defense has strict requirements on the correctness and reliability of the FPGA software, the software needs to be subjected to full simulation test before delivery. The main aim of the simulation test is to verify whether the developed program codes accord with the design expectation according to the functional requirements of the application, and the simulation test plays an increasingly important role in the design of FPGA software. FPGA simulation is generally divided into multiple levels, and the simulation attention point and the detail degree of each level are different, and according to the detail degree and the target of the simulation, the FPGA simulation can be divided into the following main levels: a. System level simulation, which is to verify the high-level function of the design, but not to relate to specific hardware implementation details; b. verifying whether the synthesized netlist accords with an expected function, including gate delay information but not including detailed time sequence information after layout and wiring, and finding out some time sequence related problems, wherein the problems are closer to actual hardware than behavior level simulation; c. The time sequence level simulation is that whether the design after layout and wiring meets the time sequence requirement or not contains detailed time sequence information, so that the design can work correctly on actual hardware, the behavior closest to the actual hardware can find out all the problems related to the time sequence, but the simulation speed is slowest, and the setting is complex. The current virtualization simulation technology develops rapidly in the fields of a CPU and an MCU, in order to achieve a better simulation effect, an attempt is made to combine FPGA simulation with the virtualization technology, but when the FPGA simulation is combined with other virtualization technologies, the problem of how the FPGA simulation is fused with a full-digital simulation system needs to be solved, in addition, the traditional FPGA simulation only outputs results aiming at level time sequences, and a more visual simulation effect cannot be provided. The patent document with publication number CN118427054A discloses a simulation method based on a communication sub-card of a vein system FC in a full digital simulation environment, which belongs to the technical field of system simulation, and comprises registering a virtual port processing function in an operating system core layer of a vein operation system; the method comprises the steps of establishing a register model of an FC communication sub-card, distributing basic functions and definitions of registers, establishing a simulation drive of the FC communication sub-card, providing an access interface of the basic functions in the simulation drive, establishing a simulation FC communication sub-card running state machine model, hanging a read-write interface of the FC communication sub-card in a virtual port processing function, registering the FC communication sub-card interface in an operating system of an operating system core layer for being called by a weather system application, and mapping the FC communication sub-card to external data receiving and transmitting and register states into the operating system of a physical machine. However, the patent document still has a defect that a relatively intuitive simulation effect cannot be provided. Disclosure of Invention Aiming at the defects in the prior art, the invention aims to provide a simulation integration method and system of an FPGA communication module. The invention provides a simulation integration method of an FPGA communication module, which comprises the following steps: S1, converting IP source codes of an FPGA communication module into FPGA simulation module codes of C++ language; Step S2, based on FPGA simulation module codes, performing interface adaptation on a system bus access part accessing an FPGA communication module in the all-digital simulation system; s3, introducing another module which is completely the same as the FPGA communication module as a symmetrical module, and carrying out cross connection of a receiving-transmit