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CN-121008837-B - Register overflow optimization method, device and storage medium

CN121008837BCN 121008837 BCN121008837 BCN 121008837BCN-121008837-B

Abstract

The embodiment of the application provides a register overflow optimization method, equipment and a storage medium, which are applied to the technical field of chips, and in the method, for each virtual register in a target program, a corresponding target register class is selected from N candidate register classes based on the physical register type supported by an instruction operand where the virtual register is positioned, wherein N is larger than 1; when the register overflows, the target register is selected from the allocated first physical registers, the instruction operand stored in the target register overflows to the second physical registers in other N-1 candidate register classes, and compared with the process that the instruction operand overflows to the memory to generate read-write operation on the memory, the application overflows to different types of physical registers, generates read-write operation on the physical registers, relieves the pressure of the registers, reduces the performance cost of overflowing to the memory, and improves the register allocation efficiency.

Inventors

  • Request for anonymity
  • Request for anonymity

Assignees

  • 上海壁仞科技股份有限公司

Dates

Publication Date
20260508
Application Date
20251027

Claims (9)

  1. 1. A method for optimizing register overflow, comprising: For each virtual register in a target program, selecting a corresponding target register class from N candidate register classes based on the physical register type supported by an instruction operand where the virtual register is located, wherein N is greater than 1; allocating a first physical register in the target register class for the virtual register; when the register overflows, selecting a target register from the allocated first physical registers, and overflowing instruction operands stored in the target register to second physical registers in other N-1 candidate register classes, wherein the method comprises the steps of selecting a first overflow register class from the N-1 candidate register classes based on the respective priority of the N-1 candidate register classes, and the priority of the candidate register class and the read-write delay attribute of the candidate register class are in negative correlation; And when the second physical registers in the available state are not contained in the first overflow register class, the first overflow register class is excluded from the N-1 candidate register classes, and the rest candidate register classes are traversed in an iterative mode until the second physical registers in the available state are obtained.
  2. 2. The method of claim 1, wherein selecting a corresponding target register class from the N candidate register classes based on a physical register type supported by an instruction operand in which the virtual register is located, comprises: And matching the N candidate register classes with the physical register types supported by the instruction operands of the virtual registers, wherein the number of the available registers meets the preset allocation condition, and taking the candidate register classes as the target register class.
  3. 3. The method of claim 1, wherein the selecting a first overflow register class from the N-1 candidate register classes based on the respective priorities of the N-1 candidate register classes comprises: And selecting a candidate register class with highest priority from the N-1 candidate register classes as the first overflow register class.
  4. 4. The method of claim 1, wherein each iteration round comprises the steps of: selecting an overflow register class from the remaining candidate register classes based on the priorities of the remaining candidate register classes; Overflowing the instruction operand stored by the target register to a second physical register when the second physical register in an available state is contained in the overflow register class; And when the overflow register class does not contain the second physical register in the available state, eliminating the overflow register class selected in the round from the rest candidate register classes, and entering the next round of iterative process.
  5. 5. The method of any one of claims 1 to 4, wherein after overflowing the instruction operand held by the target register to a second physical register in the other N-1 candidate register classes, further comprising: and reading the instruction operand from the second physical register, and executing the operation in the target program based on the instruction operand to obtain an operation result.
  6. 6. The method of claim 5, wherein after overflowing the instruction operand held by the destination register to a second physical register in the other N-1 candidate register classes, further comprising: Performing snoop optimization on a transfer instruction that overflows the instruction operands to the second physical register and reads the instruction operands from the second physical register.
  7. 7. Computer device comprising a memory, a chip and a computer program stored on the memory and running on the chip, characterized in that the chip implements the steps of the method according to any of claims 1-6 when the computer program is executed by the chip.
  8. 8. A computer readable storage medium, characterized in that it stores a computer program for execution by a computer device, which computer program, when run on the computer device, causes the computer device to perform the steps of the method according to any of claims 1-6.
  9. 9. A computer program product comprising a computer program stored on a computer readable storage medium, the computer program comprising program instructions which, when executed by a computer device, cause the computer device to carry out the steps of the method according to any one of claims 1 to 6.

Description

Register overflow optimization method, device and storage medium Technical Field The embodiment of the application relates to the technical field of chips, in particular to a register overflow optimization method, a device and a storage medium. Background In the compiling process of the program, the storage and processing of data in the physical registers are indirectly realized by allocating the physical registers (namely, variables or temporary values) to virtual registers in the program, wherein the virtual registers are temporary logic registers generated by a compiler. In the related art, a chip often supports different types of physical registers, and in a register allocation task, a corresponding register class is set first when an instruction is selected, and then physical registers in the register class are allocated to virtual registers in a program. When the physical register in the register type is insufficient, the instruction operand in the allocated physical register is overflowed to the memory to vacate the physical register, and when the instruction operand is needed to be used, the instruction operand is read from the memory. The above scheme needs to write the instruction operand into the memory and read the instruction operand from the memory, so that the efficiency of reading and writing the memory is low, and the cost of overflowing to the memory is high. Disclosure of Invention The embodiment of the invention provides a register overflow optimization method, a device and a storage medium, which are used for reducing performance overhead caused by overflow of an instruction operand into a memory. In one aspect, an embodiment of the present application provides a method for optimizing register overflow, where the method includes: For each virtual register in a target program, selecting a corresponding target register class from N candidate register classes based on the physical register type supported by an instruction operand where the virtual register is located, wherein N is greater than 1; allocating a first physical register in the target register class for the virtual register; When the register overflows, selecting a target register from the allocated first physical registers, and overflowing instruction operands stored by the target register to the second physical registers in other N-1 candidate register classes. In one aspect, an embodiment of the present application provides a register overflow optimizing apparatus, including: the selection module is used for selecting a corresponding target register class from N candidate register classes based on the physical register types supported by the instruction operands of the virtual registers aiming at each virtual register in the target program, wherein N is larger than 1; An allocation module, configured to allocate a first physical register in the target register class to the virtual register; and the overflow module is used for selecting a target register from the allocated plurality of first physical registers when the register overflows, and overflowing the instruction operand stored in the target register to the second physical registers in the other N-1 candidate register classes. Optionally, the selection module is specifically configured to: And matching the N candidate register classes with the physical register types supported by the instruction operand, wherein the number of the available registers meets the preset allocation condition, and the candidate register classes are used as the target register classes. Optionally, the overflow module is specifically configured to: Selecting a first overflow register class from the N-1 candidate register classes based on the respective priorities of the N-1 candidate register classes, wherein the priorities of the candidate register classes and the delays of the candidate register classes are in a negative correlation; and overflowing the instruction operand stored by the target register to a second physical register when the second physical register in an available state is contained in the first overflow register class. Optionally, the overflow module is specifically configured to: And selecting a candidate register class with highest priority from the N-1 candidate register classes as the first overflow register class. Optionally, the overflow module is further configured to: Excluding the first overflow register class from the N-1 candidate register classes when the second physical register in the available state is not included in the first overflow register class; traversing the rest candidate register classes in an iterative mode until a second physical register in a usable state is obtained, wherein each iteration process comprises the following steps: Selecting an overflow register class from the remaining candidate register classes based on the respective priorities of the remaining candidate register classes; Overflowing the instruction operand stored by the target