CN-121009856-B - Parameter configuration method, device, electronic equipment, storage medium and program product

Abstract

The application provides a parameter configuration method, a device, electronic equipment, a storage medium and a program product, wherein the method comprises the steps of obtaining a function description of a target chip design, obtaining a behavior level parameter model, a system level parameter model and an RTL level parameter model according to the function description, wherein the behavior level parameter model comprises a behavior level parameter, the system level parameter model comprises a system level parameter, the RTL level parameter model comprises an RTL level parameter, establishing a dependency relationship among parameters in the behavior level parameter model, the system level parameter model and the RTL level parameter model to obtain a parameter set, optimizing the parameter set according to the dependency relationship to obtain a target parameter set enabling the target chip design not to have time sequence violations, and outputting parameter configuration according to the target parameter set. The application can reduce the risk of inconsistent parameter versions, improve the reliability of parameter configuration in the chip and improve the design efficiency of the chip.

Inventors

• LIU JIAN
• PAN HONGYANG

Assignees

• 上海芯睿域智能科技有限公司

Dates

Publication Date

20260505

Application Date

20250825

Claims (20)

1. 1. A method for configuring parameters, comprising: Acquiring a functional description of a target chip design; Obtaining a behavior level parameter model, a system level parameter model and an RTL level parameter model according to the function description, wherein the behavior level parameter model comprises behavior level parameters, the system level parameter model comprises system level parameters, and the RTL level parameter model comprises RTL level parameters; establishing a dependency relationship for parameters in the behavior-level parameter model, the system-level parameter model and the RTL-level parameter model to obtain a parameter set; Optimizing the parameter set according to the dependency relationship to obtain a target parameter set which enables the target chip design to have no timing violations; And outputting parameter configuration according to the target parameter set.
2. 2. The method of claim 1, wherein deriving a system-level parametric model from the functional description comprises: Obtaining each system level parameter according to the function description; Converting each system level parameter into a data flow diagram level intermediate representation IR, a loop nesting level IR and an instruction operation level IR according to the corresponding relation with the data flow diagram, the loop nesting and the instruction operation; Orthogonalization processing is carried out on parameters corresponding to the data flow graph level IR, the loop nesting level IR and the instruction operation level IR, and the system level parameter model is obtained.
3. 3. The method of claim 1, wherein establishing a dependency relationship for parameters in the behavioral level parameter model, the system level parameter model, and the RTL level parameter model to obtain a parameter set comprises: Orthogonalizing parameters in the behavior-level parameter model, the system-level parameter model and the RTL-level parameter model; and constructing a dependency relation tree for the parameters subjected to orthogonalization processing, wherein the dependency relation tree is used for recording the dependency relation among the parameters in the behavior-level parameter model, the system-level parameter model and the RTL-level parameter model.
4. 4. The method of claim 3, wherein orthogonalizing parameters in the behavioral level parameter model, the system level parameter model, and the RTL level parameter model comprises: distributing all parameters with intersection relations among the parameters in the behavior-level parameter model, the system-level parameter model and the RTL-level parameter model into the same orthogonal subspace to obtain a plurality of orthogonal subspaces; constructing a dependency tree for the orthogonalized parameters, including: And constructing a dependency tree for parameters in each orthogonal subspace.
5. 5. The method of claim 4, wherein the dependency tree stores a range of parameter values, a strength of association, and a version identification.
6. 6. The method of claim 1, wherein prior to establishing a dependency on parameters in the behavioral level parameter model, the system level parameter model, and the RTL level parameter model, the method further comprises: and storing each parameter according to the division of the minimum functional unit, and storing only one identical parameter corresponding to the same minimum functional unit when Chu Gesuo parameters are stored.
7. 7. The method of claim 1, wherein the method further comprises: calculating hash values of various parameter combinations; the hash values of each parameter combination and each parameter combination are stored in association.
8. 8. The method of claim 1, wherein optimizing the set of parameters according to the dependency relationship comprises: Generating a configuration strategy matrix containing priority weights, optimization directions and constraint boundaries based on a preset constraint condition library; And optimizing each parameter after the dependency relationship is established according to the dependency relationship and the configuration strategy matrix.
9. 9. The method of claim 8, wherein the constraint library has recorded therein basic constraints of chip design and updated constraints for each iteration of the optimization process.
10. 10. The method of claim 8, wherein the behavioral level parameter model includes constraint information; Based on a preset constraint condition library, generating a configuration strategy matrix containing priority weights, optimization directions and constraint boundaries, wherein the configuration strategy matrix comprises the following steps: generating a configuration strategy matrix containing priority weights, optimization directions and constraint boundaries according to the constraint condition information and basic constraint conditions of chip designs in the constraint condition library, wherein the constraint condition information contains the priority weights, the optimization directions and the constraint boundaries.
11. 11. The method of claim 8, wherein the method further comprises: Performing formal verification and simulation coverage rate test on the optimized parameters; And under the condition that the verification result or the test result fails, updating the constraint conditions in the constraint condition library according to the verification result or the test result.
12. 12. The method of claim 11, wherein formal verification of the optimized parameters comprises: and adopting a calculation tree logic model checking technology to perform formal verification in the process of optimizing each parameter.
13. 13. The method of claim 11, wherein performing a simulated coverage test on the optimized parameters comprises: Generating a test case through a preset assertion library, wherein the assertion library records input and output when simulation fails in each iteration process of an optimization process; And using the test case to perform simulation coverage rate test on the optimized parameters.
14. 14. The method of claim 1, wherein deriving a behavioral level parameter model from the functional description comprises: Extracting behavior level characteristics according to the function description, wherein the behavior level characteristics characterize characteristics related to functions to be realized by the target chip design in the function description; and constructing and obtaining a behavior-level parameter model according to the behavior-level characteristics.
15. 15. The method of claim 14, wherein extracting behavioral level characteristics from the functional description comprises: and processing the functional description by adopting a natural language model to obtain the behavior-level characteristics.
16. 16. The method of claim 14, wherein after constructing a behavioral level parametric model from the behavioral level characteristics, the method further comprises: Legalization analysis is carried out on the behavior-level parameter model by using a static time sequence analysis engine; and under the condition that the constraint condition information of the behavior-level parameter model is illegal, updating the constraint condition information of the behavior-level parameter model.
17. 17. The method according to any one of claims 1 to 16, wherein the parameter set obtained after the establishment of the dependency relationship has a plurality of parameter combination spaces, and each parameter combination space contains parameters with the dependency relationship; Optimizing each parameter after the dependency relationship is established, including: Global parameter tuning is carried out on the parameter combination space, and a Pareto front solution set is obtained; Respectively carrying out gradient optimization on Pareto front solution sets of the parameter combination spaces; And repeating the above process until obtaining each parameter with optimal area and power consumption when no time sequence violation exists.
18. 18. The method of claim 17, wherein, Global parameter tuning is performed on the parameter combination space, and the global parameter tuning comprises the following steps: Determining a key parameter combination space, wherein the key parameter combination space is a parameter combination space which is sensitive to parameter adjustment currently in all parameter combination spaces; global parameter tuning is carried out on the key parameter combination space; Correspondingly, the gradient optimization is carried out on Pareto front solution sets of the parameter combination spaces respectively, and the method comprises the following steps: and respectively carrying out gradient optimization on Pareto front solution sets of the key parameter combination spaces.
19. 19. The method of claim 17, wherein the Pareto front solution set obtained retains only non-dominant solutions.
20. 20. The method of claim 17, wherein during each iteration, reducing the magnitude of adjustment of parameters involved in the timing violation path during the previous iteration; the timing violation path is a path with timing violations found when the chip design is verified in the iterative process.

Description

Parameter configuration method, device, electronic equipment, storage medium and program product Technical Field The present application relates to the field of chip design technologies, and in particular, to a parameter configuration method, a parameter configuration device, an electronic device, a storage medium, and a program product. Background In the field of integrated circuit design, the existing technology for parameter configuration of each programmable module in a chip mainly adopts a hierarchical independent optimization and static templating method, and mainly comprises independent optimization of parameters of three layers of behavior-level parameters, system-level parameters and RTL (REGISTER TRANSFER LEVEL ) parameters. However, at present, each abstraction level (behavior level, system level, RTL level) adopts an independent optimization strategy, and a cross-level parameter association mechanism is lacked. This results in manual synchronization of configuration in multiple levels for cross-level parameter adjustment, which is very prone to inconsistent parameter versions, affecting chip design efficiency. For example, a line size (a behavior-level parameter) defined by a behavior level cannot be automatically mapped to a burst transmission length parameter (a system-level parameter) of a DDR (Double Data Rate) controller at a system level, and RTL-level wiring congestion information (an RTL-level parameter) cannot be reversely transferred to a NoC (Network-on-Chip) topology decision module at the system level to perform parameter update in the NoC topology decision module. Disclosure of Invention An embodiment of the application aims to provide a parameter configuration method, a device, electronic equipment, a storage medium and a program product, which are used for improving the reliability of parameter configuration of a chip. The embodiment of the application provides a parameter configuration method, which comprises the steps of obtaining a function description of a target chip design, obtaining a behavior level parameter model, a system level parameter model and an RTL level parameter model according to the function description, wherein the behavior level parameter model comprises a system level parameter, the RTL level parameter model comprises an RTL level parameter, establishing a dependency relationship among parameters in the behavior level parameter model, the system level parameter model and the RTL level parameter model to obtain a parameter set, optimizing the parameter set according to the dependency relationship to obtain a target parameter set enabling the target chip design to have no time sequence violations, and outputting parameter configuration according to the target parameter set. In the implementation scheme, the dependency relationship is established on the parameters in the behavior-level parameter model, the system-level parameter model and the RTL-level parameter model, and then the parameter set is optimized according to the dependency relationship, so that when the behavior-level parameter, the system-level parameter and the RTL-level parameter are optimized, due to the existence of the dependency relationship, when any one of the behavior-level parameter, the system-level parameter and the RTL-level parameter with the dependency relationship is adjusted, the parameters of other related levels are correspondingly adjusted, and therefore automatic cross-level parameter adjustment is achieved. For example, with the implementation scheme, the line size of the behavior-level parameter cache will be automatically mapped to the burst transmission length parameter of the DDR controller at the system level, and the adjustment of the RTL-level wiring congestion information will also be reversely transferred to the NoC topology decision module at the system level to update the parameters in the NoC topology decision module. Therefore, the risk of inconsistent parameter versions can be reduced, the reliability of parameter configuration in the chip can be improved, and the chip design efficiency can be improved. Optionally, obtaining a system level parameter model according to the function description comprises obtaining each system level parameter according to the function description, converting each system level parameter into a data flow diagram level IR (INTERMEDIATE REPRESENTATION ), a loop nesting level IR and an instruction operation level IR according to the corresponding relation with a data flow diagram, loop nesting and instruction operation, and carrying out orthogonalization processing on parameters corresponding to the data flow diagram level IR, the loop nesting level IR and the instruction operation level IR to obtain the system level parameter model. In the implementation manner, aiming at the system-level parameters, the system-level parameters are converted into the data flow diagram level IR (INTERMEDIATE REPRESENTATION ), the loop nesting level IR