CN-121031479-B - Digital circuit simulation test method and system

CN121031479BCN 121031479 BCN121031479 BCN 121031479BCN-121031479-B

Abstract

The invention discloses a digital circuit simulation test method and system, wherein the method comprises the following steps of S1, constructing a circuit simulation model, establishing a plurality of simulation transmission chains for simulation input ends and simulation output ends of the circuit simulation model, performing corresponding time sequence labeling to obtain time sequence labeling information of the simulation transmission chains, S2, setting a plurality of simulation transmission sections of the simulation transmission chains, establishing simulation branched chains of each simulation transmission section to establish transmission section transmission channels, combining the label information of the simulation transmission sections to obtain simulation transmission section combination information, S3, obtaining a preset test excitation file, performing segment test of a plurality of simulation transmission sections for the simulation transmission chains, performing state judgment of time length residual information and test residual information in each test process, and performing test time length adjustment according to judgment results to obtain adjustment time length.

Inventors

ZHANG BOYU
ZENG XIANGBIN

Assignees

华中科技大学

Dates

Publication Date: 20260508
Application Date: 20250819

Claims (8)

1. The digital circuit simulation test method is characterized by comprising the following steps of: S1, constructing a circuit simulation model, and establishing a plurality of simulation transmission chains for a simulation input end and a simulation output end of the circuit simulation model and performing corresponding time sequence annotation to obtain time sequence annotation information of the simulation transmission chains; s2, setting a plurality of simulation transmission segments of a simulation transmission chain, establishing a simulation branched chain of each simulation transmission segment to establish a transmission segment transmission channel, and combining the marking information of the simulation transmission segments to obtain combination information of the simulation transmission segments; Dividing each simulation transmission chain into a plurality of simulation transmission segments, wherein each simulation transmission segment represents a specific logic or functional unit in a circuit; S3, acquiring a preset test excitation file, carrying out segment test on a plurality of simulation transmission segments on the simulation transmission chain, judging the states of the duration residual information and the test residual information in each segment of test process, and carrying out test duration adjustment according to the judging result to obtain adjustment duration; Wherein, step S2 includes: s2.1, arranging a plurality of simulation transmission sections on a simulation transmission chain, and establishing a simulation branched chain for a transmission section output end and a simulation output end of each simulation transmission section; S2.2, establishing a transmission section transmission channel of each simulation transmission section through the simulation branched chain pair corresponding to the simulation transmission section and the simulation output end; S2.3, marking each simulation transmission segment to obtain marking information of the simulation transmission segment; S2.4, acquiring the marking information of the simulation transmission section of each simulation output end through the simulation output end; S2.5, combining the simulated transmission segment marking information of the plurality of simulated output ends through the simulated output ends to obtain simulated transmission segment combination information; S2.6, acquiring a plurality of simulation transmission segment combination information of the simulation transmission chain of different time sequence marking information through the simulation transmission segment combination information.
2. The digital circuit simulation test method according to claim 1, wherein in step S1: s1.1, acquiring circuit hardware information of a digital circuit to be tested, and acquiring a hardware description language according to the circuit hardware information; s1.2, describing and modeling a digital circuit to be tested through the hardware description language to obtain a circuit simulation model; S1.3, acquiring a simulation input end and a simulation output end of a circuit simulation model; S1.4, acquiring preset simulation time sequence information, and establishing a time sequence simulation signal transmission relation for a simulation input end and a simulation output end according to the preset simulation time sequence information to acquire a plurality of simulation transmission chains of the preset simulation time sequence information; S1.5, performing time sequence labeling on the simulation transmission chains through preset simulation time sequence information, and obtaining time sequence labeling information of each simulation transmission chain.
3. A digital circuit simulation test method according to any of claims 1-2, wherein step S3 comprises: S3.1, acquiring a preset test excitation file, and extracting characteristics of test signals from the preset test excitation file to acquire a plurality of test characteristic signals; s3.2, segmenting a preset test excitation file according to a plurality of test characteristic signals to obtain a plurality of test excitation file test segments; s3.3, distributing a plurality of test excitation file test segments according to the simulation transmission segments and the simulation transmission segment combination information to obtain transmission matching test segments corresponding to the simulation transmission segments and transmission matching combination test segments corresponding to the simulation transmission segment combination information; S3.4, performing simulation test duration distribution on the simulation transmission section to obtain simulation test duration distribution information; s3.5, inputting a transmission matching test section of a preset test excitation file and a transmission matching combination test section of the preset test excitation file into a simulation transmission chain corresponding to the time sequence label for simulation test; s3.6, acquiring information used by the simulation test duration, adjusting the simulation test duration distribution information according to all the information of the simulation test duration, acquiring test duration adjustment information of the simulation transmission segment, and adjusting the test duration of the corresponding simulation transmission segment according to the test duration adjustment information; S3.7, acquiring single-segment test information of transmission matching test segments of each simulation transmission segment and multi-segment combination test information of transmission matching combination test segments of simulation transmission segment combination information through a simulation output end.
4. The digital circuit simulation test method according to claim 3, wherein in step S3.4, the simulation test duration allocation is performed on the simulation transmission segment to obtain simulation test duration allocation information, and the method specifically includes: s3.4.1, calculating corresponding simulation test duration according to a preset excitation file; s3.4.2, acquiring transmission matching test section information of the simulation transmission section, and calculating test section test duration of each transmission matching test section according to the simulation test duration; S3.4.3, performing simulation test on the simulation transmission chain according to the test duration of the test section to obtain simulation test process information; s3.4.4, acquiring the information used by the simulation test duration of the current simulation test section according to the simulation test process information.
5. A digital circuit simulation test method according to claim 3, wherein step 3.5 specifically comprises: s3.5.1, acquiring the test section test duration and the information used by the simulation test duration of the current simulation test section, calculating the difference value of the test section test duration and the information used by the simulation test duration, and acquiring the duration residual information of the current simulation test section; S3.5.2, judging the duration utilization state of the simulation test section according to the duration residual information of the simulation test section, and obtaining duration utilization state judgment information; S3.5.3, acquiring transmission matching test section information and actual test information of the current simulation test section, calculating a difference value between the transmission matching test section information and the actual test information, and acquiring test residual information of the current simulation test section; s3.5.4, performing time length adjustment judgment on the simulation test section according to the time length residual information and the test residual information to obtain time length adjustment judgment information; S3.5.5, calculating a time length adjustment coefficient of the current simulation test section according to the time length adjustment judgment information, and adjusting the time length of the current simulation test section according to the time length adjustment coefficient of the current simulation test section to obtain the adjustment time length of the current simulation test section; s3.5.6, acquiring the remaining test duration according to the adjustment duration of the current simulation test segment, and adjusting the duration of the simulation test end according to the remaining test duration to acquire the adjustment duration of the remaining simulation test segment.
6. The method according to claim 5, wherein in step S3.5.2, when the time length remaining information is positive, the positive state determination is performed on the time length utilization state of the simulation test section, and when the time length remaining information is 0, the negative state determination is performed on the time length utilization state of the simulation test section.
7. The method of claim 5, wherein in step S3.5.4, if the duration utilization determination information of the current simulation test segment is in a positive state, the duration adjustment determination information is in a positive state, the current simulation test segment is not adjusted, and if the duration utilization determination information of the current simulation test segment is in a negative state, the duration adjustment determination information is in a negative state, the current simulation test segment is adjusted.
8. A digital circuit simulation test system for performing the method of any of claims 1-7, the system comprising the following modules: the transmission quantity construction module is used for constructing a circuit simulation model, establishing a plurality of simulation transmission chains for a simulation input end and a simulation output end of the circuit simulation model and carrying out corresponding time sequence annotation to obtain time sequence annotation information of the simulation transmission chains; the transmission segment splitting and combining module is used for setting a plurality of simulation transmission segments of a simulation transmission chain, establishing a simulation branched chain of each simulation transmission segment so as to establish a transmission segment transmission channel, and combining the marking information of the simulation transmission segments to obtain simulation transmission segment combination information; The segment test adjusting module is used for acquiring a preset test excitation file, carrying out segment test on a plurality of simulation transmission segments of the simulation transmission chain, judging the states of the duration residual information and the test residual information in each segment of test process, and adjusting the test duration according to the judging result to obtain the adjustment duration.

Description

Digital circuit simulation test method and system Technical Field The invention belongs to the technical field of digital circuit simulation test, and particularly provides a digital circuit simulation test method and a digital circuit simulation test system. Background As digital circuit design complexity increases, conventional simulation test methods face multiple challenges. The traditional digital circuit simulation test is generally based on an integral test, and is difficult to test functions or logics singly or in combination, so that the flexibility of the test is low, the pertinence is lacked, the test precision is low, the simulation test abnormality is difficult to position efficiently, the test duration is difficult to adjust flexibly, and the efficiency and the precision cannot be achieved. The Chinese patent publication No. CN1235278C discloses a general digital circuit simulation test system and a test method, and the patent has the advantages of strong universality, high code multiplexing rate and high expandability, but has the problems of low test efficiency and low precision. Disclosure of Invention Aiming at the problems existing in the prior art, the invention provides a digital circuit simulation test method and a digital circuit simulation test system. The invention adopts the following technical scheme: A digital circuit simulation test method comprises the following steps: S1, constructing a circuit simulation model, and establishing a plurality of simulation transmission chains for a simulation input end and a simulation output end of the circuit simulation model and performing corresponding time sequence annotation to obtain time sequence annotation information of the simulation transmission chains; s2, setting a plurality of simulation transmission segments of a simulation transmission chain, establishing a simulation branched chain of each simulation transmission segment, further establishing a transmission segment transmission channel, and combining the marking information of the simulation transmission segments to obtain combination information of the simulation transmission segments; s3, acquiring a preset test excitation file, carrying out segment test on a plurality of simulation transmission segments on the simulation transmission chain, judging the states of the duration residual information and the test residual information in each segment of test process, and carrying out test duration adjustment according to the judging result to obtain adjustment duration. Preferably, in step S1: s1.1, acquiring circuit hardware information of a digital circuit to be tested, and acquiring a hardware description language according to the circuit hardware information; s1.2, describing and modeling a digital circuit to be tested through the hardware description language to obtain a circuit simulation model; S1.3, acquiring a simulation input end and a simulation output end of a circuit simulation model; S1.4, acquiring preset simulation time sequence information, and establishing a time sequence simulation signal transmission relation for a simulation input end and a simulation output end according to the preset simulation time sequence information to acquire a plurality of simulation transmission chains of the preset simulation time sequence information; S1.5, performing time sequence labeling on the simulation transmission chains through preset simulation time sequence information, and obtaining time sequence labeling information of each simulation transmission chain. Preferably, step S2 includes: s2.1, arranging a plurality of simulation transmission sections on a simulation transmission chain, and establishing a simulation branched chain for a transmission section output end and a simulation output end of each simulation transmission section; S2.2, establishing a transmission section transmission channel of each simulation transmission section through the simulation branched chain pair corresponding to the simulation transmission section and the simulation output end; S2.3, marking each simulation transmission segment to obtain marking information of the simulation transmission segment; S2.4, acquiring the marking information of the simulation transmission section of each simulation output end through the simulation output end; S2.5, combining the simulated transmission segment marking information of the plurality of simulated output ends through the simulated output ends to obtain simulated transmission segment combination information; S2.6, acquiring a plurality of simulation transmission segment combination information of the simulation transmission chain of different time sequence marking information through the simulation transmission segment combination information. Preferably, step S3 includes: S3.1, acquiring a preset test excitation file, and extracting characteristics of test signals from the preset test excitation file to acquire a plurality of test characteristic signals