CN-121078772-B - Trench MOSFET device with low on-resistance and method for manufacturing same

CN121078772BCN 121078772 BCN121078772 BCN 121078772BCN-121078772-B

Abstract

The invention provides a trench MOSFET device with low on resistance and a preparation method thereof, the trench MOSFET device with low on resistance comprises a heavily doped first conductive type substrate, a first conductive type epitaxial layer is arranged on the first conductive type substrate, a single cell trench is arranged in an active region, a second conductive type well region and a first conductive type injection layer are arranged on the top of the first conductive type epitaxial layer between adjacent single cell trenches from bottom to top, a gate oxide layer is arranged on the inner wall of the single cell trench, grid polysilicon is arranged in the single cell trench, a bowl-shaped first conductive type buried layer wrapping the U-shaped bottom of the single cell trench is formed below the bottom of the single cell trench, and a bowl-shaped second conductive type buried layer wrapping the U-shaped bottom of the single cell trench is formed in the first conductive type buried layer below the bottom of the single cell trench.

Inventors

GE WEI
DING LEI
TENG ZHIGANG

Assignees

无锡商甲半导体有限公司

Dates

Publication Date: 20260512
Application Date: 20250909

Claims (6)

1. A trench MOSFET device with low on-resistance comprises an active region and a terminal protection region arranged around the active region, wherein the trench MOSFET device with low on-resistance comprises a heavily doped first conductive type substrate (1), a first conductive type epitaxial layer (2) is arranged on the first conductive type substrate (1), the surface of the first conductive type epitaxial layer (2) facing away from the first conductive type substrate (1) is a first main surface, the surface of the first conductive type substrate (1) facing away from the first conductive type epitaxial layer (2) is a second main surface, The active region is provided with single-cell grooves (4) in the first conductive type epitaxial layer (2), each single-cell groove (4) is arranged in parallel at intervals, a second conductive type well region (9) and a first conductive type injection layer (10) are arranged at the top of the first conductive type epitaxial layer (2) between every two adjacent single-cell grooves (4) from bottom to top, the single-cell grooves (4) extend into the lower part of the second conductive type well region (9) from the first main surface, the inner wall of each single-cell groove (4) is provided with a gate oxide layer (7), the single-cell grooves (4) are provided with gate polysilicon (801), and the gate polysilicon (801) is insulated from the first conductive type injection layer (10), the second conductive type well region (9) and the first conductive type epitaxial layer (2) through the gate oxide layer (7); A bowl-shaped first conductive type buried layer (5) wrapping the U-shaped bottom of the single cell groove is formed below the bottom of the single cell groove (4), and a bowl-shaped second conductive type buried layer (6) wrapping the U-shaped bottom of the single cell groove is formed in the first conductive type buried layer (5) below the bottom of the single cell groove (4); the implantation dosage of the second conductivity type impurity for forming the second conductivity type buried layer (6) is higher than the implantation dosage of the first conductivity type impurity for forming the first conductivity type buried layer (5); an insulating medium layer (11) is arranged above the first main surface, a source metal (13) and a gate metal are arranged above the insulating medium layer (11), the source metal (13) is connected with a first conductive type injection layer (10) and a second conductive type well region (9) between adjacent unit cell grooves (4) through a source contact hole (1201) penetrating through the insulating medium layer (11) and the first conductive type injection layer (10), and the gate metal is connected with gate polysilicon (801) in the unit cell grooves (4) through a gate contact hole penetrating through the insulating medium layer (11); A drain metal is arranged on the second main surface; the first conductivity type impurity used for forming the first conductivity type buried layer (5) is phosphorus, and the implantation dosage is 4E14cm < -2 > -7E 14cm < -2 >; the second conductivity type impurity used for forming the second conductivity type buried layer (6) is boron, and the implantation dosage is 8E15cm < -2 > -9E 15cm < -2 >.
2. The trench MOSFET device with low on-resistance of claim 1, The width of the first conductive type buried layer (5) is 1.3-1.8 times of the width of the unit cell groove (4).
3. The trench MOSFET device with low on-resistance of claim 1, The width of the second conductive type buried layer (6) is 1-1.2 times of the width of the unit cell groove (4).
4. A method for manufacturing a trench MOSFET device with low on-resistance according to any one of claims 1 to 3, comprising the steps of: Step S1, providing a heavily doped first conductive type substrate (1), and growing a first conductive type epitaxial layer (2) on the first conductive type substrate (1), wherein the surface of the first conductive type epitaxial layer (2) facing away from the first conductive type substrate (1) is a first main surface, and the surface of the first conductive type substrate (1) facing away from the first conductive type epitaxial layer (2) is a second main surface; S2, depositing a hard mask layer on the first main surface, coating photoresist on the hard mask layer, forming a photoresist groove pattern through photoetching, etching the hard mask layer to form a hard mask (3), etching the first conductive type epitaxial layer (2) to form a single cell groove (4) by using the hard mask (3) as a blocking layer, and depositing or growing a sacrificial oxide layer on the inner wall of the single cell groove (4); s3, using a hard mask (3) as a blocking layer, injecting first conductivity type impurities into the bottom of the single cell groove (4) through a three-time high-energy ion injection process, and forming a bowl-shaped first conductivity type buried layer (5) below the bottom of the single cell groove (4) to wrap the U-shaped bottom of the single cell groove; Forming the upper left part of the first conductive type buried layer (5); Forming a middle part of a buried layer (5) of a first conductivity type; forming the upper right part of the first conductive type buried layer (5); S4, taking the hard mask (3) as a blocking layer, injecting second conductivity type impurities into the bottom of the single cell groove (4), and forming a bowl-shaped second conductivity type buried layer (6) wrapping the U-shaped bottom of the single cell groove in the first conductivity type buried layer (5) below the bottom of the single cell groove (4); S5, removing the hard mask through an etching process, and removing the sacrificial oxide layer through wet etching; Step S6, depositing conductive polysilicon on the first main surface, and carrying out polysilicon back etching by utilizing a dry etching and chemical mechanical polishing process to form grid polysilicon (801) in the unit cell groove (4); Step S7, injecting second conductivity type impurities into the first main surface and pushing a well, forming a second conductivity type well region (9) at the top of the first conductivity type epitaxial layer (2), then selectively injecting the first conductivity type impurities and annealing, and forming a first conductivity type injection layer (10) at the top of the first conductivity type epitaxial layer (2) between adjacent unit cell grooves (4); S8, depositing an insulating medium layer (11) on the first main surface and carrying out reflow to enable the surface to be flat; Step S9, selectively etching the insulating dielectric layer (11) and the first conductive type epitaxial layer (2) to form a gate contact hole and a source contact hole (1201); step S10, injecting second conductivity type impurities into the bottoms of the gate contact hole and the source contact hole (1201) and performing high-temperature rapid annealing; Depositing a layer of metal titanium and titanium nitride film on the inner walls of the gate contact hole and the source contact hole (1201) to react with silicon to generate low-resistance titanium silicide, and filling metal tungsten into each contact hole; Step S11, depositing metal on the first main surface and selectively etching to form source metal (13) and gate metal; The source metal (13) is connected with the first conductive type injection layer (10) and the second conductive type well region (9) between the adjacent unit cell grooves (4) through a source contact hole (1201) penetrating through the insulating dielectric layer (11) and the first conductive type injection layer (10); the gate metal is connected with gate polysilicon (801) in the unit cell groove (4) through a gate contact hole penetrating through the insulating dielectric layer (11); step S12, carrying out a back thinning process on the second main surface, and then depositing drain metal; In the step S3, the first conductivity type impurity used for forming the first conductivity type buried layer (5) is phosphorus, and the implantation dosage is 4E14cm < -2 > -7E 14cm < -2 >; In the step S4, the second conductivity type impurity used for forming the second conductivity type buried layer (6) is boron, and the implantation dosage is 8E15cm < -2 > to 9E15cm < -2 >.
5. The method of manufacturing a trench MOSFET device having a low on-resistance as recited in claim 4, In the step S3, the width of the first conductive type buried layer (5) is 1.3-1.8 times of the width of the unit cell groove (4).
6. The method of manufacturing a trench MOSFET device having a low on-resistance as recited in claim 4, In the step S4, the width of the second conductive type buried layer (6) is 1-1.2 times of the width of the unit cell groove (4).

Description

Trench MOSFET device with low on-resistance and method for manufacturing same Technical Field The invention relates to the field of semiconductor power devices, in particular to a trench MOSFET device with low on-resistance and a preparation method thereof. Background Along with the development of new energy automobiles, industrial robots and artificial intelligence, china power semiconductor devices are rapidly developed in different application fields. MOSFET devices are one type of power semiconductor devices. The higher the integration level of the device, the power consumption is always one of the focuses of the power semiconductor device, and the most effective method for reducing the power consumption is to reduce the on-resistance of the device. Many efforts have been made by researchers to reduce the on-resistance of trench MOSFET devices. The first method optimizes the on-resistance by optimizing the parameters of the device; researchers such as tension research the optimal values of the on-resistance of the device under different withstand voltages, and mainly discuss the influence of the width of the grooves and the spacing of the grooves on the on-resistance, and experimental results show that the on-resistance of the groove MOSFET with high withstand voltage is much closer to the ideal value than that of the low-voltage MOSFET. The second method optimizes the on-resistance by optimizing the device structure. Researchers such as Zhang Yue have proposed an improved superjunction UMOS that achieves a reduction in on-resistance by introducing a P-pillar of varying doping concentration. Researchers have also proposed a UMOS structure with a floating P-type region that can effectively reduce the on-resistance of the device. Both of these structures also sacrifice a portion of the breakdown voltage. These approaches can effectively reduce the on-resistance of the device, but the breakdown voltage is also reduced simultaneously, and finally only a compromise relationship between the two is sought. At present, products such as super junction MOSFETs and split gate MOSFETs exist, and the on-resistance and the power consumption of the device are reduced, but the super junction MOSFETs and the split gate MOSFETs are naturally more expensive than UMOS due to the fact that the manufacturing process is more complex than UMOS. Disclosure of Invention In order to solve at least one technical problem in the prior art, the embodiment of the invention provides a trench MOSFET device with low on-resistance and a preparation method thereof, which can reduce the on-resistance without reducing breakdown voltage and obviously increasing cost. In order to achieve the technical purpose, the technical scheme adopted by the embodiment of the invention is as follows: In a first aspect, an embodiment of the invention provides a trench MOSFET device with low on-resistance, which comprises an active area and a terminal protection area arranged around the active area, wherein the trench MOSFET device with low on-resistance comprises a heavily doped first conductive type substrate, a first conductive type epitaxial layer is arranged on the first conductive type substrate, the surface of the first conductive type epitaxial layer, which is away from the first conductive type substrate, is a first main surface, and the surface of the first conductive type substrate, which is away from the first conductive type epitaxial layer, is a second main surface; The active region is provided with unit cells in the first conductive type epitaxial layer, each unit cell is arranged in parallel at intervals, the top of the first conductive type epitaxial layer between every two adjacent unit cells is provided with a second conductive type well region and a first conductive type injection layer from bottom to top, the unit cells extend into the lower part of the second conductive type well region from the first main surface, the inner wall of each unit cell is provided with a gate oxide layer, and gate polysilicon is arranged in each unit cell and insulated from the first conductive type injection layer, the second conductive type well region and the first conductive type epitaxial layer through the gate oxide layer; Forming a bowl-shaped first conductive type buried layer wrapping the U-shaped bottom of the single cell groove below the bottom of the single cell groove; The implantation dose of the second conductivity type impurity for forming the second conductivity type buried layer is higher than the implantation dose of the first conductivity type impurity for forming the first conductivity type buried layer; An insulating dielectric layer is arranged above the first main surface, and a source metal and a grid metal are arranged above the insulating dielectric layer; the source metal is connected with the first conductive type injection layer and the second conductive type well region between adjacent unit cell grooves through a source conta