CN-121126857-B - Preparation method of semiconductor device and semiconductor device

Abstract

The application provides a preparation method of a semiconductor device and the semiconductor device, which are applied to BCD (Bipolar-CMOS-DMOS), namely, bipolar transistor (Bipolar), complementary Metal Oxide Semiconductor (CMOS) and Diffusion Metal Oxide Semiconductor (DMOS) are integrated on the same chip. The method comprises the steps of forming a shallow trench on a semiconductor substrate, filling a first material in the shallow trench, forming a deep trench in part of the shallow trench, depositing a second material in the deep trench, wherein the second material and the first material are different insulating filling materials, and in a subsequent etching process, the different insulating filling materials have different etching rates, so that gaps appear in contact areas of the shallow trench and the deep trench due to the different etching rates, and the stability of a device is affected. Therefore, the top area of the deep trench is formed into an etching back area, and the third material is deposited in the etching back area, so that the same material is deposited in the overlapping area of the deep trench and the shallow trench. Thus, defects existing in the manufacturing process of the semiconductor device are reduced.

Inventors

• CUI WEIGANG

Assignees

• 杭州富芯半导体有限公司

Dates

Publication Date

20260512

Application Date

20251112

Claims (11)

1. 1. A method of manufacturing a semiconductor device, the method comprising: Providing a semiconductor substrate, forming a passivation oxide layer and a first hard mask layer on the semiconductor substrate, starting etching on the first hard mask layer until reaching a first preset position on the semiconductor substrate, forming a shallow trench, and filling a first material into the shallow trench; removing the first hard mask layer and reserving the passivation oxide layer; Depositing a second hard mask layer on the passivation oxide layer; Starting etching at a position corresponding to part of the shallow trenches on a second hard mask layer through an etching process until reaching a second preset position on an epitaxial layer of the semiconductor substrate, forming deep trenches, and depositing a second material in the deep trenches, wherein the second material is different from the first material; etching the second material filled in the top region of the deep trench to a set depth to form an etching back region, and depositing a third material in the etching back region, wherein the etching back region is an overlapping region of the shallow trench and the deep trench; and removing the third material on the semiconductor substrate, and stopping the removing process to the second hard mask layer.
2. 2. The method as recited in claim 1, further comprising: forming the shallow trench on the semiconductor substrate by photoetching and etching; depositing a first material on the semiconductor substrate for forming the shallow trench, wherein the deposited first material at least fills the shallow trench; Removing the first material on the semiconductor substrate through etching and/or grinding processes, and stopping the removing process on the first hard mask layer.
3. 3. The method as recited in claim 1, further comprising: defining a region where the deep trench needs to be formed through a photoetching process; Performing an etching process, and forming deep trenches penetrating through part of the shallow trenches in the areas corresponding to part of the shallow trenches; The photoresist is removed.
4. 4. The method of claim 3, wherein depositing a second material within the deep trench comprises: And depositing the second material on the surface of the second hard mask layer and in the deep trench by adopting a chemical vapor deposition mode.
5. 5. The method of claim 4, further comprising, after obtaining the filled deep trench and the first insulating layer formed of the second material: and removing the second material on the semiconductor substrate through etching and/or chemical mechanical polishing, and stopping the removing process to the second hard mask layer.
6. 6. The method of claim 1, wherein depositing a third material in the etch-back region comprises: and depositing the third material on the etching-back area and the surface of the second hard mask layer by adopting a high-density plasma chemical vapor deposition mode.
7. 7. The method of claim 1, wherein removing the third material on the semiconductor substrate further comprises: and removing the third material on the semiconductor substrate through etching and/or chemical mechanical polishing.
8. 8. The method as recited in claim 7, further comprising: and removing the second hard mask layer and retaining the passivation oxide layer.
9. 9. The method of claim 1, further comprising, prior to depositing a second material within the deep trench: forming a side wall oxide layer on the side wall surface of the deep trench; and etching the bottom of the deep trench and performing ion implantation at the bottom.
10. 10. The method as recited in claim 9, further comprising: And filling polycrystalline silicon on the passivation oxide layer.
11. 11. A semiconductor device prepared according to any one of claims 1-10, comprising: the semiconductor substrate, shallow trench that forms on the semiconductor substrate, in the shallow trench of part the shallow trench in formation, it is filled with first material to fill in the shallow trench, it is filled with the second material to fill in the deep trench, at the top of deep trench with shallow trench's overlap area is filled and is different from the third material of second material.

Description

Preparation method of semiconductor device and semiconductor device Technical Field The application relates to the field of semiconductor manufacturing, in particular to a preparation method of a semiconductor device and the semiconductor device. Background BCD (Bipolar-CMOS-DMOS) is a special semiconductor manufacturing process that integrates Bipolar transistors (bipolars), complementary Metal Oxide Semiconductors (CMOS), and Diffused Metal Oxide Semiconductors (DMOS) onto the same chip to achieve a combination of high performance analog circuits, digital control, and high voltage high current drive capability. Deep Trench Isolation (DTI) is a technique used in integrated circuit fabrication to achieve electrical Isolation between different devices by etching deep trenches into a silicon wafer and filling with insulating material. Shallow trench isolation structures (Shallow Trench Isolation, STI) are used to electrically isolate components by etching relatively shallow trenches into the surface of a silicon wafer and filling the trenches with an insulating material. In the prior art, the steps existing in the manufacturing process of the semiconductor device are complex, and the parameters for performing chemical mechanical polishing in the process are smaller, so that crystal defects are caused, and relatively high current still passes when the transistor is in the off state. Therefore, how to reduce defects existing in the manufacturing process of semiconductor devices is a technical problem to be solved. Disclosure of Invention The embodiment of the application provides a preparation method of a semiconductor device, which can reduce defects existing in the preparation process of the semiconductor device. The embodiment of the application also provides a semiconductor device. The specific scheme is as follows: In a first aspect, an embodiment of the application provides a method for manufacturing a semiconductor device, which includes providing a semiconductor substrate, forming a shallow trench on the semiconductor substrate, filling a first material in the shallow trench, forming a deep trench in a part of the shallow trench, depositing a second material in the deep trench, wherein the second material is different from the first material, forming an etching-back region in a top region of the deep trench filled with the second material, and depositing a third material in the etching-back region, wherein the etching-back region is an overlapping region of the shallow trench and the deep trench. Optionally, forming a shallow trench on the semiconductor substrate, filling a first material in the shallow trench, including forming a passivation oxide layer and a first hard mask layer on an epitaxial layer of the semiconductor substrate, forming the shallow trench on the semiconductor substrate by photolithography and etching, depositing the first material on the semiconductor substrate forming the shallow trench, at least filling the shallow trench with the deposited first material, removing the first material on the semiconductor substrate by etching and/or grinding, and stopping the removing process on the first hard mask layer. Optionally, the method further comprises removing the first hard mask layer and retaining the passivation oxide layer. Optionally, a second hard mask layer is deposited on the passivation oxide layer and the surface of the shallow trench, a deep trench is formed in part of the shallow trench, the deep trench is defined by a photoetching process, an etching process is performed, a deep trench penetrating part of the shallow trench is formed in a region corresponding to part of the shallow trench, and photoresist is removed. Optionally, the depositing the second material in the deep trench includes depositing the second material on the surface of the second hard mask layer and in the deep trench by chemical vapor deposition. Optionally, after obtaining the filled deep trench and the first insulating layer formed of the second material, removing the second material on the semiconductor substrate by etching and/or chemical mechanical polishing, and stopping the removing process to the second hard mask layer. Optionally, forming an etching-back region in the top region of the deep trench filled with the second material, and depositing the third material in the etching-back region includes etching the second material filled in the top region of the deep trench to a set depth to form the etching-back region. Optionally, the method further comprises the step of depositing the third material on the etching-back area and the surface of the second hard mask layer by adopting a high-density plasma chemical vapor deposition mode. Optionally, the third material and the first material are the same material. Optionally, after the filled etching-back region and the second insulating layer formed by the third material are obtained, removing the third material on the semiconductor substrate by etc