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CN-121149029-B - Method for evaluating feature size of semiconductor device

CN121149029BCN 121149029 BCN121149029 BCN 121149029BCN-121149029-B

Abstract

The invention relates to the technical field of self-aligned patterning technology, in particular to a method for evaluating the feature size of a semiconductor device. The method comprises the steps of placing a wafer in a partition chuck, processing the wafer through a self-aligned patterning process to obtain a plurality of empty slots, in an oxide etching step, enabling the temperature difference of any two partitions of the partition chuck to be larger than zero, enabling the highest temperature to be higher than or equal to a reference temperature and the lowest temperature to be lower than or equal to the reference temperature, obtaining the characteristic dimension balance degree of the wafer corresponding to each partition, and determining the size relation between the characteristic dimension of a core area and the characteristic dimension of a gap at the reference temperature according to the temperature of each partition of the partition chuck and the corresponding characteristic dimension balance degree. The evaluation method of the semiconductor device feature size can rapidly determine the feature size relation between the core area and the gap of the wafer, improves the process debugging efficiency, reduces the process debugging cost and has high conclusion accuracy.

Inventors

  • YANG LICHENG

Assignees

  • 北京集成电路装备创新中心有限公司

Dates

Publication Date
20260512
Application Date
20250819

Claims (10)

  1. 1. A method of evaluating a feature size of a semiconductor device, the method comprising: In the oxide etching step of the self-aligned patterning process, the temperature difference of any two subareas of the subarea chuck is larger than zero, the highest temperature of the subarea chuck is higher than or equal to the reference temperature, and the lowest temperature of the subarea chuck is lower than or equal to the reference temperature, wherein the empty grooves comprise core areas and gaps, the characteristic size of the gaps is positively correlated with the temperature of the corresponding subareas on the subarea chuck after the self-aligned patterning process is completed, and the characteristic size of each core area is basically consistent with the characteristic size of the core area formed when the subarea chuck adopts the reference temperature in the oxide etching step; the method comprises the steps of obtaining the characteristic dimension balance degree of each partition corresponding to the wafer, wherein the characteristic dimension balance degree is the absolute value of the characteristic dimension difference value of two adjacent empty slots; Determining, namely determining the size relation between the characteristic size of the core area and the characteristic size of the gap at the reference temperature according to the temperature of each partition of the partition chuck and the corresponding characteristic size balance degree; And sequencing the characteristic dimension balances according to the temperatures of the corresponding subareas from low to high, determining that the characteristic dimension of the core area is larger than the characteristic dimension of the gap at the reference temperature if the characteristic dimension balances gradually decrease, and determining that the characteristic dimension of the core area is smaller than the characteristic dimension of the gap at the reference temperature if the characteristic dimension balances gradually increase.
  2. 2. The method of claim 1, wherein a plurality of the partitions are radially distributed from the center of the partition chuck from inside to outside, and the temperatures of the plurality of the partitions gradually decrease or increase from inside to outside.
  3. 3. The method of evaluating a feature size of a semiconductor device according to claim 2, wherein a temperature of the partition located at the innermost portion coincides with the reference temperature.
  4. 4. The method of evaluating a feature size of a semiconductor device of claim 3, wherein the determining step comprises: If the characteristic dimension balance degree gradually decreases from the center of the wafer to the edge or increases after the characteristic dimension is gradually decreased from the center of the wafer to the edge, the characteristic dimension of the core region is smaller than the characteristic dimension of the gap at the reference temperature; and under the condition that the temperature of the partition chuck gradually increases from inside to outside, if the characteristic dimension balance degree gradually decreases from the center of the wafer to the edge or increases after the characteristic dimension balance degree is firstly decreased, determining that the characteristic dimension of the core area is larger than the characteristic dimension of the gap at the reference temperature, and if the characteristic dimension balance degree gradually increases from the center of the wafer to the edge, determining that the characteristic dimension of the core area is larger than the characteristic dimension of the gap at the reference temperature.
  5. 5. The method of claim 1, wherein the plurality of partitions includes a center partition, a middle inner partition, a middle outer partition, and an edge partition sequentially distributed from a center of the partition chuck from inside to outside in a radial direction.
  6. 6. The method of claim 1, wherein the temperature difference between adjacent two zones of the zone chuck is less than or equal to 5 ℃.
  7. 7. The method of claim 6, wherein the temperature difference between adjacent two zones of the zone chuck is 4 ℃.
  8. 8. The method for evaluating the feature sizes of semiconductor devices according to any one of claims 1 to 7, wherein the obtaining step comprises: Measuring the characteristic sizes of a plurality of empty slots, and determining the corresponding relation between the characteristic sizes of the empty slots and the measuring positions; Dividing two adjacent empty slots into a group according to the corresponding relation; And respectively carrying out difference on the characteristic sizes of the two empty slots in each group and taking absolute values to obtain a plurality of characteristic size balances and corresponding positions.
  9. 9. The method of evaluating a feature size of a semiconductor device according to claim 8, wherein the acquiring step comprises: and measuring the characteristic dimension of the empty slot by utilizing a characteristic dimension scanning electron microscope.
  10. 10. A method of evaluating a feature size of a semiconductor device, the method comprising: The method comprises the steps of processing a wafer in a chuck, and processing the wafer through a self-aligned patterning process to obtain a plurality of empty slots, wherein in an oxide etching step of the self-aligned patterning process, the temperature of the chuck is higher than or lower than a reference temperature, the empty slots comprise a core area and a gap, after the self-aligned patterning process is completed, the characteristic dimension of the gap is positively related to the temperature of the chuck, and the characteristic dimension of the core area is basically consistent with the characteristic dimension of the core area formed when the chuck adopts the reference temperature in the oxide etching step; The method comprises the steps of obtaining the characteristic dimension balance degree of the wafer, wherein the characteristic dimension balance degree is the absolute value of the characteristic dimension difference value of two adjacent empty slots; determining, according to the temperature of the chuck and the characteristic dimension balance degree, a size relation between the characteristic dimension of the core region and the characteristic dimension of the gap at the reference temperature; If the temperature of the chuck is lower than the reference temperature, the characteristic size balance degree of the core area is lower than the characteristic size balance degree of the gap at the reference temperature if the characteristic size balance degree of the chuck is lower than the characteristic size balance degree at the reference temperature; And under the condition that the temperature of the chuck is higher than the reference temperature, if the characteristic dimension balance degree after temperature adjustment is lower than the characteristic dimension balance degree at the reference temperature, the characteristic dimension of the core area is larger than the characteristic dimension of the gap at the reference temperature, and if the characteristic dimension balance degree after temperature adjustment is higher than the characteristic dimension balance degree at the reference temperature, the characteristic dimension of the core area is smaller than the characteristic dimension of the gap at the reference temperature.

Description

Method for evaluating feature size of semiconductor device Technical Field The invention relates to the technical field of self-aligned patterning technology, in particular to a method for evaluating the feature size of a semiconductor device. Background SADP (Self-Aligned Double Patterning, self-aligned double patterning technology) and SAQP (Self-Aligned Quadruple Patterning, self-aligned quad patterning technology) are used as advanced multiple lithography technologies, which can realize high resolution and small feature size, and thus can improve the integration level and performance of chips. In actual process debugging, due to the influence of factors such as CD (feature size), open ratio, etch amountand the like, deviations between Core CD (feature size of Core region) and Gap CD (feature size of Gap) are caused, and finally, the feature size balance (imbalance, abbreviated as IMB) between Core and Gap is deteriorated, so that it is critical to determine CD problems in process debugging, and subsequent IMB improvement needs to be performed based on the conditions. In the related art, CD problems are determined by observing wafer slices by TEM (transmission electron microscopy), which is not only time-consuming but also costly. Disclosure of Invention The invention aims to provide a method for evaluating the feature size of a semiconductor device, so as to alleviate the technical problems of long time consumption and high cost in determining CD problems in the related art. The invention provides a method for evaluating the characteristic dimension of a semiconductor device, which comprises the following steps: In the oxide etching step of the self-aligned patterning process, the temperature difference of any two subareas of the subarea chuck is larger than zero, the highest temperature of the subarea chuck is higher than or equal to the reference temperature, and the lowest temperature of the subarea chuck is lower than or equal to the reference temperature; The method comprises the steps of obtaining the characteristic dimension balance degree of each partition corresponding to the wafer, wherein the characteristic dimension balance degree is the absolute value of the characteristic dimension difference value of two adjacent empty slots, and each empty slot comprises a core area and a gap; And determining, namely determining the size relation between the characteristic dimension of the core region and the characteristic dimension of the gap at the reference temperature according to the temperature of each partition of the partition chuck and the corresponding characteristic dimension balance degree. Preferably, as an implementation manner, a plurality of the partitions are distributed radially from the center of the partition chuck from inside to outside, and the temperatures of the partitions gradually decrease or increase from inside to outside. Preferably, as an implementation manner, the temperature of the innermost partition is consistent with the reference temperature. Preferably, as an implementation manner, the determining step includes: If the characteristic dimension balance degree gradually decreases from the center of the wafer to the edge or increases after the characteristic dimension is gradually decreased from the center of the wafer to the edge, the characteristic dimension of the core region is smaller than the characteristic dimension of the gap at the reference temperature; and under the condition that the temperature of the partition chuck gradually increases from inside to outside, if the characteristic dimension balance degree gradually decreases from the center of the wafer to the edge or increases after the characteristic dimension balance degree is firstly decreased, determining that the characteristic dimension of the core area is larger than the characteristic dimension of the gap at the reference temperature, and if the characteristic dimension balance degree gradually increases from the center of the wafer to the edge, determining that the characteristic dimension of the core area is larger than the characteristic dimension of the gap at the reference temperature. Preferably, as an implementation manner, the plurality of partitions include a center partition, a middle inner partition, a middle outer partition and an edge partition, which are sequentially distributed from the center of the partition chuck from inside to outside along a radial direction. Preferably, as an implementation manner, the temperature difference between two adjacent subareas of the subarea chuck is less than or equal to 5 ℃. Preferably, as an implementation, the temperature difference between two adjacent partitions of the partition chuck is 4 ℃. Preferably, as an implementation manner, the obtaining step includes: Measuring the characteristic sizes of a plurality of empty slots, and determining the corresponding relation between the characteristic sizes of the empty slots and the measuring positi