CN-121152125-B - PCB ESD protection method based on composite TVS and honeycomb grounding

Abstract

The invention discloses a PCB ESD protection method based on composite TVS and honeycomb grounding, which comprises the following steps of S100, coping with external input impact layout; step 200, TVS array layout; step S300, honeycomb grounding structure layout; step S400, PCB lamination layout, step S500, establishing a static electricity discharge special path: according to the invention, the ESD protection efficiency of the frequency band above 3GHz is up to 96%, the ESD protection level is raised to +/-30 kV, the high-voltage external impact can be stably protected, and the over-current voltage capability is effectively improved by adopting a honeycomb grounding structure and the size of the honeycomb.

Inventors

• YU TAO
• GONG WEI
• HAO CHUNHUA

Assignees

• 青岛汉泰电子有限公司

Dates

Publication Date

20260508

Application Date

20251011

Claims (4)

1. 1. The PCB ESD protection method based on the composite TVS and the honeycomb grounding is characterized by comprising the following specific steps: step S100, coping with external input impact layout; Blocking external 30kV initial energy impact received at the interface by adopting a high-pressure gas discharge tube at the interface; step S200, TVS array layout, comprising: a first level TVS array layout and a second level TVS array layout, wherein, A 30kW ultra-high power first-stage TVS array is arranged at a position which is less than or equal to 5mm away from the low-speed interface or less than or equal to 3mm away from the high-speed interface; matching parameters of the first stage TVS array, comprising: Setting the junction capacitance to be 0.75pF; Setting breakdown voltage to be more than or equal to 24V; Setting the peak pulse current to be more than or equal to 100A; setting the response time to be less than or equal to 0.5ns; Connecting a TVS array grounding pin with a honeycomb grounding area through a short straight line; The front end of the IC is provided with a low-capacitance second-stage TVS array, residual voltage is clamped, and the IC is protected; Matching parameters of the second-stage TVS array, comprising: setting the distance between the second-stage TVS array and the IC to be more than or equal to 15mm; Setting the distance between the first-stage TVS array and the second-stage TVS array to be more than or equal to 10mm; Step S300, honeycomb grounding structure layout; the hexagonal grid spacing between the first-stage TVS array and the second-stage TVS array is set to 20 mil-30 mil, and the grid coverage rate is more than or equal to 85%; Setting the unit cell impedance to be less than 0.1 omega, and setting the grid line width to be more than or equal to 10mil; step 301, an independent grounding island is arranged at an interface and is connected with a main ground plane through a honeycomb via hole; step S302, directly connecting a metal shell and a honeycomb grounding structure by a gas discharge tube close to an interface; step S303, adopting a star topology direct connection honeycomb grounding structure for TVS array grounding pins; Step S400, a PCB stacking layout, comprising: An interface signal layer directly connecting the TVS array with the honeycomb grounding structure; the honeycomb grounding layer adopts 50% copper coverage rate and is encrypted through grids; an inner layer signal layer, a control interface signal layer; The planar layer is interconnected with the honeycomb grounding structure through a via hole array, wherein a 3 multiplied by 3 via hole array is arranged around the grounding end of the TVS array, the density of the via holes of the whole plate is more than or equal to 1/cm < 2 >, the aperture is 0.3mm, and the interval is 2mm; The power layer is slotted to isolate a high-voltage area and a low-voltage area; step S500, establishing a static electricity discharge special path: step S501, connecting an interface, a TVS array, an IC and a PCB layer with a digital grounding column in a single point manner, and adding 100nF high-voltage capacity to the connecting point; step S502, densely placing grounding through holes near the grounding pins of the ESD protection device, and connecting the grounding through holes to the internal ground plane, so as to further reduce the inductance of the grounding path.
2. 2. The method for protecting the PCB ESD based on the composite TVS and the honeycomb ground of claim 1, wherein the TVS array layout further comprises: and (3) carrying out solder mask windowing, wherein green oil is not covered on the periphery of the TVS array bonding pad within 0.5 mm.
3. 3. The method of claim 1 wherein the capacitance of the low capacitance second stage TVS array is <1pF.
4. 4. The PCB ESD protection method based on the composite TVS and the honeycomb ground of claim 1, wherein the matching of the high voltage isolation parameters comprises: the distance between the high-pressure area and the low-pressure area is more than or equal to 10mm; and isolating the interface signal layer by adopting a 2mm slot, and filling insulating paint.

Description

PCB ESD protection method based on composite TVS and honeycomb grounding Technical Field The invention relates to the technical field of static electricity discharge, in particular to a PCB ESD protection method based on composite TVS and honeycomb grounding. Background The response time of the traditional TVS diode (such as US20170256923A 1) is more than or equal to 1ns, ns-level ESD pulse is difficult to protect, the size of a PCB is increased due to the fact that the grounding area is simply increased, and parasitic capacitance (> 5 pF) is introduced by ESD protection in a high-frequency circuit to influence signal integrity; ESD causes great trouble to the field of circuit design, such as direct short circuit, open circuit or loss of function of devices, direct damage to hard disk, flash memory, etc. to result in data loss or file damage ‌, increased maintenance cost ‌, frequent replacement of damaged elements or repair equipment, such as a USB interface capacitor short circuit, to replace TVS tube ‌, reduced ‌ production efficiency ‌, equipment failure shutdown or increased test procedures. The ESD protection is also related to the electronic devices laid out on the PCB circuit board, which is the most easily ignored aspect in ESD protection, and for the instruments such as oscilloscopes and signal generators, which require accurate measurement of values, the current ESD protection method uses TVS diodes as protection means, and referring to fig. 1, the current TVS diodes are used as ESD protection means, and some simple antistatic measures (such as magnetic rings) are added, so that only ±15kV external voltage impact can be protected. However, for external high-voltage impact of +/-30 kV, the ESD protection is not in place, and the repeated test shows that the problems that (1) the ESD protection efficiency of the frequency band above 3GHz is less than 60 percent, and (2) the qualification rate of the existing scheme of +/-30 kV air discharge is less than 85 percent exist. Therefore, the prior art cannot meet the needs of people at present, and based on the present situation, improvement on the prior art is needed. Disclosure of Invention The invention aims to provide a PCB ESD protection method based on composite TVS and honeycomb grounding, so as to solve the problems in the prior art. The invention provides a PCB ESD protection method based on composite TVS and honeycomb grounding, which comprises the following specific steps: step S100, coping with external input impact layout; the external 30kV initial energy impact received at the interface is blocked by adopting a high-pressure gas discharge tube at the interface. Step S200, TVS array layout, comprising: a first level TVS array layout and a second level TVS array layout, wherein, A 30kW ultra-high power first-stage TVS array is arranged at a position which is less than or equal to 5mm away from the low-speed interface or less than or equal to 3mm away from the high-speed interface; and a low-capacitance second-stage TVS array is arranged at the front end of the IC, and the residual voltage is clamped to protect the IC. Step S300, honeycomb grounding structure layout; the hexagonal grid spacing between the first-stage TVS array and the second-stage TVS array is set to 20 mil-30 mil, and the grid coverage rate is more than or equal to 85%; Setting the unit cell impedance to be less than 0.1 omega, and setting the grid line width to be more than or equal to 10mil; step 301, an independent grounding island is arranged at an interface and is connected with a main ground plane through a honeycomb via hole; step S302, directly connecting a metal shell and a honeycomb grounding structure by a gas discharge tube close to an interface; step S303, the TVS array grounding pin adopts a star topology direct connection honeycomb grounding structure. Step S400, a PCB stacking layout, comprising: An interface signal layer directly connecting the TVS array with the honeycomb grounding structure; the honeycomb grounding layer adopts 50% copper coverage rate and is encrypted through grids; an inner layer signal layer, a control interface signal layer; The plane layer is interconnected with the honeycomb grounding structure through the via hole array; the power layer is slotted to isolate a high voltage area from a low voltage area. Step S500, establishing a static electricity discharge special path: step S501, connecting an interface, a TVS array, an IC and a PCB layer with a digital grounding column in a single point manner, and adding 100nF high-voltage capacity to the connecting point; step S502, densely placing grounding through holes near the grounding pins of the ESD protection device, and connecting the grounding through holes to the internal ground plane, so as to further reduce the inductance of the grounding path. The invention has the following beneficial effects that the ESD protection efficiency of the frequency band above 3GHz reaches 96%, the ESD pr