CN-121166467-B - Memory module detection circuit, method, device and medium

CN121166467BCN 121166467 BCN121166467 BCN 121166467BCN-121166467-B

Abstract

The invention discloses a storage module detection circuit, a method, a device and a medium, and relates to the technical field of storage module detection. The circuit comprises a data communication module, a data analysis and verification module, an interface control module, a data communication module, a data analysis and verification module and a data communication module, wherein the data analysis and verification module is electrically connected with the data communication module, the interface control module is respectively electrically connected with the data communication module and the data analysis and verification module, the data communication module is used for receiving a data packet sent by a host and sending the data packet conforming to a protocol to the data analysis and verification module, the data analysis and verification module is used for analyzing the data packet to obtain an analysis result, the interface control module is used for carrying out reading operation or writing operation on a storage module according to the analysis result and receiving a response result of the storage module, the data analysis and verification module is used for verifying the response result to obtain a verification result and sending the verification result to the data communication module, and the data communication module is also used for sending the verification result to the host. The circuit can realize detection and result feedback of the memory module through simple commands.

Inventors

CHEN JUNYU
YAN ZHIYU
HAN JUN
ZHAN LIANYANG

Assignees

珠海航宇微科技股份有限公司

Dates

Publication Date: 20260508
Application Date: 20251120

Claims (7)

1. A memory module detection circuit, comprising: a data communication module; The data analysis and verification module is electrically connected with the data communication module; the interface control module is respectively and electrically connected with the data communication module and the data analysis and verification module; The data communication module is used for receiving a data packet sent by a host and sending the data packet conforming to a protocol to the data analysis and verification module, the data analysis and verification module is used for analyzing the data packet to obtain an analysis result, the interface control module is used for performing read operation or write operation on a storage module according to the analysis result and receiving a response result of the storage module, the data analysis and verification module is also used for verifying the response result to obtain a verification result and sending the verification result to the data communication module, and the data communication module is also used for sending the verification result to the host; The data communication module includes: The receiving response unit is used for responding to the triggering command of the host, receiving the data packet, analyzing a frame header in the data packet, sending storage unit selection information contained in the frame header to the interface control module, converting serial data in the data packet into parallel data, and sending the parallel data to the data analysis and verification module; the receiving response unit is used for receiving the verification result from the host, and is electrically connected with the receiving response unit; the data analysis and verification module comprises: The data generation unit is used for analyzing the data packet to obtain an analysis result and sending the analysis result to the interface control module; The data verification unit is used for verifying the response result to obtain a verification result and sending the verification result to the data communication module; The counter is respectively and electrically connected with the data generating unit and the data checking unit and is used for controlling the working states of the data generating unit and the data checking unit; The data generation unit comprises a transmission module and multiple paths of parallel data selection modules, each path of data selection module comprises a first reverser and a first selector, the input end of the first reverser is connected with input data of the data packet, the output end of the first reverser is electrically connected with the first input end of the first selector, the second input end of the first selector is connected with the input data of the data packet, the output end of the first selector is electrically connected with the input end of the transmission module, the output end of the transmission module is electrically connected with the interface control module, and the controlled end of the first selector is also electrically connected with the counter.
2. The memory module detection circuit of claim 1, wherein the data verification unit comprises: the data caching unit is used for receiving the response result; The buffer register is electrically connected with the data buffer unit and is used for buffering the response result; the second negation device is electrically connected with the cache register and is used for negating the response result; The second selector is electrically connected with the counter, the buffer register and the second negation device respectively and is used for selecting the response result and the negated response result according to the instruction of the counter; And the comparison module is used for comparing the output data of the second selector with the output data of the first selector and sending the comparison result to the data communication module.
3. The memory module detection circuit of claim 1, wherein the interface control module comprises: The third selector is used for acquiring storage unit selection information in the data packet, generating a chip selection signal according to the storage unit selection information and sending the chip selection signal to the storage module; The interface time sequence control unit is used for performing read operation or write operation on the storage module according to the analysis result; the data receiving unit is used for obtaining the response result and sending the response result to the data analysis and verification module.
4. A memory module detection method applied to the memory module detection circuit according to any one of claims 1 to 3, the method comprising: The data communication module is used for receiving the data packet sent by the host computer and sending the data packet conforming to the protocol to the data analysis and verification module; Analyzing the data packet through the data analysis verification module to obtain an analysis result; Performing read operation or write operation on the storage module through the interface control module according to the analysis result, and receiving a response result of the storage module; the response result is checked through the data analysis and check module, a check result is obtained, and the check result is sent to the data communication module; and sending the verification result to the host through the data communication module.
5. The method according to claim 4, wherein the receiving, by the data communication module, the data packet sent by the host and sending the data packet conforming to the protocol to the data parsing and checking module, includes: Responding to a triggering instruction of the host, enabling the data communication module to receive and analyze the frame header of the data packet; When the data packet accords with a protocol, the data communication module sends the storage unit selection information contained in the frame header to the interface control module, converts serial data in the data packet into parallel data and sends the parallel data to the data analysis and verification module.
6. A memory module detection apparatus comprising a memory module detection circuit as claimed in any one of claims 1 to 3.
7. A storage medium storing computer-executable instructions for causing a computer to perform the storage module detection method of any one of claims 4-5.

Description

Memory module detection circuit, method, device and medium Technical Field The present invention relates to the field of computer manufacturing technology, and in particular, to a storage module detection circuit, a method, an apparatus, and a medium. Background In the working process of the storage module, the conditions such as data damage or error code and the like can possibly occur, and in order to ensure the data integrity and stable operation of the system, the storage module needs to be detected by a detection module to judge whether abnormal conditions such as data bit overturning, read interference and the like exist. At present, when the detection module detects the storage module, the detection module needs to carry out complex control on the storage module according to the time sequence requirement and the complex instruction of the storage module, and the operation process is complex. Disclosure of Invention The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, the invention provides a memory module detection circuit, a method, a device and a medium, which can simplify the detection process of a memory module. In a first aspect, a memory module detection circuit according to an embodiment of the present invention includes: a data communication module; The data analysis and verification module is electrically connected with the data communication module; the interface control module is respectively and electrically connected with the data communication module and the data analysis and verification module; The data communication module is used for receiving a data packet sent by a host and sending the data packet conforming to a protocol to the data analysis and verification module, the data analysis and verification module is used for analyzing the data packet to obtain an analysis result, the interface control module is used for performing reading operation or writing operation on the storage module according to the analysis result and receiving a response result of the storage module, the data analysis and verification module is also used for verifying the response result to obtain a verification result and sending the verification result to the data communication module, and the data communication module is also used for sending the verification result to the host. According to some embodiments of the invention, the data communication module comprises: The receiving response unit is used for responding to the triggering command of the host, receiving the data packet, analyzing a frame header in the data packet, sending storage unit selection information contained in the frame header to the interface control module, converting serial data in the data packet into parallel data, and sending the parallel data to the data analysis and verification module; the result caching unit is electrically connected with the receiving response unit and is used for caching the verification result; the receiving response unit is further configured to send the verification result cached by the result caching unit to the host. According to some embodiments of the invention, the data parsing verification module includes: The data generation unit is used for analyzing the data packet to obtain an analysis result and sending the analysis result to the interface control module; The data verification unit is used for verifying the response result to obtain a verification result and sending the verification result to the data communication module; And the counter is respectively and electrically connected with the data generating unit and the data checking unit and is used for controlling the working states of the data generating unit and the data checking unit. According to some embodiments of the invention, the data generating unit includes a transmitting module and multiple parallel data selecting modules, each data selecting module includes a first inverter and a first selector, an input end of the first inverter is connected to input data of the data packet, an output end of the first inverter is electrically connected to a first input end of the first selector, a second input end of the first selector is connected to the input data of the data packet, an output end of the first selector is electrically connected to an input end of the transmitting module, an output end of the transmitting module is electrically connected to the interface control module, and a controlled end of the first selector is also electrically connected to the counter. According to some embodiments of the invention, the data verification unit comprises: the data caching unit is used for receiving the response result; The buffer register is electrically connected with the data buffer unit and is used for buffering the response result; the second negation device is electrically connected with the cache register and is used for negating the response result; The second selector is elec