CN-121194505-B - Preparation method of bipolar element-CMOS-DMOS semiconductor device and semiconductor device

CN121194505BCN 121194505 BCN121194505 BCN 121194505BCN-121194505-B

Abstract

The application provides a preparation method of a bipolar element-CMOS-DMOS semiconductor device and the semiconductor device, wherein the method comprises the steps of providing a semiconductor substrate, and forming a bipolar element-CMOS-DMOS device region on the semiconductor substrate; and forming a double-groove structure comprising a first groove used for a shallow groove isolation structure and a second groove used for a deep groove isolation structure between any two of the bipolar element, the CMOS and the DMOS device regions, wherein the second groove is positioned in the first groove and has a depth larger than that of the first groove, and filling isolation materials in the double-groove structure to form the isolation structure of the bipolar element-CMOS-DMOS device. Compared with the traditional method, the method simplifies the process flow for forming the isolation structure, thereby reducing the influence on the bipolar element-CMOS-DMOS device. Therefore, the method can reduce defects in the preparation process of the bipolar element-CMOS-DMOS semiconductor device, and further improve the stability of the formed semiconductor device.

Inventors

CUI WEIGANG
CHEN SHUILIANG
WU JIANBO

Assignees

杭州富芯半导体有限公司

Dates

Publication Date: 20260512
Application Date: 20251120

Claims (6)

1. A method for manufacturing a bipolar element-CMOS-DMOS semiconductor device, said method comprising: providing a semiconductor substrate, wherein a bipolar element-CMOS-DMOS device region is formed on the semiconductor substrate; Forming a double-trench structure comprising a first trench for a shallow trench isolation structure and a second trench for a deep trench isolation structure between any two of the bipolar element, the CMOS and the DMOS device regions, wherein the second trench is positioned in the first trench and has a depth greater than that of the first trench; Filling isolation materials in the double-groove structure to form an isolation structure of the bipolar element-CMOS-DMOS device; Wherein the forming a dual trench structure including a first trench for a shallow trench isolation structure and a second trench for a deep trench isolation structure comprises: Forming a second passivation oxide layer and a second hard mask layer on an epitaxial layer of the semiconductor substrate, etching the second hard mask layer, forming the second trench on the semiconductor substrate, removing the second hard mask layer and the second passivation oxide layer, reforming a third passivation oxide layer and a third hard mask layer on the epitaxial layer of the semiconductor substrate, and performing an etching process on the third hard mask layer in a preset area corresponding to the top position of the second trench, and forming the first trench on the epitaxial layer of the semiconductor substrate.
2. The method of claim 1, wherein filling the dual trench structure with an isolation material comprises: And depositing an insulating material in the double-trench structure, wherein the deposited insulating material at least fills the double-trench structure, and the method comprises the steps of filling the double-trench structure with the deposited insulating material, and depositing an insulating material layer on the surface of the third hard mask layer and the surface of the double-trench top area.
3. The method of claim 1, wherein filling the dual trench structure with an isolation material comprises: Depositing an insulating material in the double-groove structure, wherein the deposited insulating material forms a gap at the central axis of the double-groove structure, and the deposited insulating material comprises an insulating material side wall layer positioned on the inner side wall of the double-groove structure and an insulating material layer positioned on the surface of a third hard mask layer on the semiconductor substrate; Etching the bottom of a second groove in the double-groove structure and implanting ions at the bottom; and forming an insulating material oxide layer corresponding to the insulating material at the gap, wherein the formed insulating material oxide layer at least fills the gap.
4. The method as recited in claim 2, further comprising: Sequentially removing the insulating material layer and the third hard mask layer on the semiconductor substrate, wherein the removing process is stopped to the third passivation oxide layer; and filling polycrystalline silicon on the third passivation oxide layer.
5. A method according to claim 3, further comprising: sequentially removing the insulating material oxide layer, the insulating material layer and the third hard mask layer on the semiconductor substrate, wherein the removing process is stopped to the third passivation oxide layer; and filling polycrystalline silicon on the third passivation oxide layer.
6. A bipolar component-CMOS-DMOS semiconductor device fabricated by the method of any of claims 1 to 5, comprising: a semiconductor substrate, a bipolar element-CMOS-DMOS device region formed on the semiconductor substrate; Forming a double-groove structure comprising a first groove used for a shallow groove isolation structure and a second groove used for a deep groove isolation structure between any two of the bipolar element, the CMOS and the DMOS device regions, wherein the second groove is positioned in the first groove and has a depth larger than that of the first groove; and filling an isolation material in the double-trench structure to form an isolation structure of the bipolar element-CMOS-DMOS device.

Description

Preparation method of bipolar element-CMOS-DMOS semiconductor device and semiconductor device Technical Field The application relates to the field of semiconductor manufacturing, in particular to a preparation method of a bipolar element-CMOS-DMOS semiconductor device and the semiconductor device. Background BCD (Bipolar-CMOS-DMOS) is a special semiconductor manufacturing process that integrates Bipolar transistors (bipolars), complementary Metal Oxide Semiconductors (CMOS), and Diffused Metal Oxide Semiconductors (DMOS) onto the same chip to achieve a combination of high performance analog circuits, digital control, and high voltage high current drive capability. In the prior art, after a BCD device region is formed on a semiconductor substrate, a deep trench is formed between any two device regions of a bipolar element, a CMOS and a DMOS, and insulating materials are filled in the deep trench, so that different device regions are physically separated, and leakage and latch-up effects between the device regions are avoided. In the above process, after the BCD device region is formed, the deep trench isolation structure is formed. The deep trench isolation structure is formed by a plurality of process steps, which is easy to affect the formed BCD device and causes device defects. Therefore, how to reduce defects existing in the manufacturing process of semiconductor devices is a technical problem to be solved. Disclosure of Invention The application provides a preparation method of a bipolar element-CMOS-DMOS semiconductor device, which can reduce defects existing in the preparation process of the semiconductor device. The application also provides a bipolar element-CMOS-DMOS semiconductor device. The specific scheme is as follows: The application provides a preparation method of a bipolar element-CMOS-DMOS semiconductor device, which comprises the steps of providing a semiconductor substrate, forming a bipolar element-CMOS-DMOS device region on the semiconductor substrate, forming a double-groove structure between any two of the bipolar element, CMOS and DMOS device regions, wherein the double-groove structure comprises a first groove used for a shallow groove isolation structure and a second groove used for a deep groove isolation structure, the second groove is located in the first groove and has a depth larger than that of the first groove, and filling isolation materials in the double-groove structure to form the isolation structure of the bipolar element-CMOS-DMOS device. . The application provides a bipolar element-CMOS-DMOS semiconductor device, which comprises a semiconductor substrate, a bipolar element-CMOS-DMOS device region, a double-trench structure, a first trench and a second trench, wherein the first trench is used for a shallow trench isolation structure, the second trench is used for a deep trench isolation structure, the second trench is located in the first trench, the depth of the second trench is larger than that of the first trench, isolation materials are filled in the double-trench structure, and the isolation structure of the bipolar element-CMOS-DMOS device is formed between any two of the bipolar element, the CMOS and the DMOS device region. Compared with the prior art, the application has the following advantages: The preparation method of the bipolar element-CMOS-DMOS semiconductor device comprises the steps of providing a semiconductor substrate, forming a bipolar element-CMOS-DMOS device region on the semiconductor substrate, forming a double-groove structure between any two of the bipolar element, CMOS and DMOS device regions, wherein the double-groove structure comprises a first groove used for a shallow groove isolation structure and a second groove used for a deep groove isolation structure, the second groove is located in the first groove and has a depth larger than that of the first groove, and filling isolation materials in the double-groove structure to form the isolation structure of the bipolar element-CMOS-DMOS device. When the dual-trench isolation structure is prepared, a dual-trench structure comprising a shallow trench and a deep trench is formed by adopting a dual-damascene process mode, and then an isolation material is filled in the dual-trench structure to form the isolation structure of the bipolar element-CMOS-DMOS device. Compared with the traditional method, the method simplifies the process flow contained in the forming process and the filling process of the double-groove structure, thereby reducing the influence on the bipolar element-CMOS-DMOS device in the forming process of the isolation structure and reducing the number of the defect of the device. Therefore, the method can reduce defects in the preparation process of the bipolar element-CMOS-DMOS semiconductor device, and further improve the stability of the formed semiconductor device. Drawings Fig. 1 is a flowchart of a method for manufacturing a bipolar element-CMOS-DMOS semiconductor device