CN-121218681-B - Deep trench field effect transistor and preparation method thereof

CN121218681BCN 121218681 BCN121218681 BCN 121218681BCN-121218681-B

Abstract

The invention provides a deep trench field effect transistor and a preparation method thereof, comprising the steps of forming a P-type layer and an N-type layer in an N-type substrate; forming a gate trench and a terminal trench, forming an N-type source region by ion implantation, forming a gate oxide layer in the trench, forming a first polysilicon layer, a thick oxide layer and a second polysilicon layer in the trench, depositing a dielectric layer, forming a drain contact region, a source contact region, a gate contact region and a terminal contact region, and forming a source electrode, a gate electrode and a drain electrode, wherein the source electrode is simultaneously connected with the N-type source region and the terminal contact region. The source contact area is arranged in the terminal area, and is realized by only directly etching the dielectric layer and the substrate below the dielectric layer, so that the process controllability is high, the steps are simple, and the etching process of the source contact area has higher stability.

Inventors

YANG XUGANG
TIAN YUEJIAO

Assignees

深圳市创飞芯源半导体有限公司

Dates

Publication Date: 20260508
Application Date: 20251128

Claims (15)

1. A method for fabricating a deep trench field effect transistor, wherein the deep trench field effect transistor comprises a termination region and an active region, the method comprising: Providing an N-type substrate, forming a P-type layer on the surface layer of the N-type substrate through a first ion implantation process, and forming an N-type layer on the surface layer of the P-type layer through a second ion implantation process; etching the active region and the terminal region to form a gate trench and a terminal trench respectively, wherein the gate trench and the terminal trench penetrate through the N-type layer and extend into the P-type layer; Forming a barrier layer of a P-type layer shielding a gate contact region in the gate trench, forming an N-type source region below the gate trench by ion implantation, wherein the N-type source region extends from the lower part of the gate trench into the N-type substrate, and removing the barrier layer; Forming a gate oxide layer in the gate trench and the termination trench; Forming a gate stack structure of a first polysilicon layer, a thick oxide layer and a second polysilicon layer in the gate trench and the terminal trench, wherein the thick oxide layer is also formed on the side wall between the second polysilicon layer and the gate trench and between the second polysilicon layer and the terminal trench; Depositing a dielectric layer on the N-type layer; etching and removing the dielectric layer in a first area of the active area to form a drain contact area, wherein the drain contact area exposes the N-type layer; Etching the dielectric layer and the gate stack structure in a second region of the active region and a terminal trench region of the terminal region to form a gate contact region and a terminal contact region, wherein the gate contact region and the terminal contact region penetrate through the second polysilicon layer and the thick oxide layer and extend into the first polysilicon layer; etching the dielectric layer, the N-type layer, the P-type layer and the N-type substrate in a terminal area to form a source contact area, wherein the source contact area extends into the N-type substrate, and the source contact area is positioned at one side of the terminal contact area far away from the gate trench; Depositing a metal layer on the dielectric layer and in the terminal contact region, the source contact region, the gate contact region and the drain contact region, and patterning the metal layer to form a source electrode, a gate electrode and a drain electrode respectively, wherein the source electrode is simultaneously connected with the terminal contact region and the source contact region; Forming the gate stack structure includes: filling a first polysilicon layer in the gate trench and the terminal trench and etching the first polysilicon layer to a depth within the gate trench and the terminal trench to expose tops of the gate trench and the terminal trench, wherein the top surface of the etched first polysilicon layer is higher than the interface between the N-type layer and the P-type layer; Forming a thick oxide layer on the surface of the first polysilicon layer and the top side walls of the gate trench and the terminal trench; And depositing a second polysilicon layer on the tops of the gate trench and the terminal trench, and carrying out planarization treatment on the second polysilicon layer to remove the second polysilicon layer on the surface of the N-type layer.
2. The method of manufacturing a deep trench FET of claim 1, wherein the N-type substrate has a resistivity of 1-100 ohm cm and a thickness of 1.5-10 μm, the first ion implantation process implants ions including boron at a dose of 1e12cm -2 ~1e14cm -2 and an implantation energy of 300-2000 kev to form a P-type layer on the N-type substrate surface, and the second ion implantation process implants ions including phosphorus at a dose of 1e12cm -2 ~1e14cm -2 and an implantation energy of 200-500 kev to form an N-type layer on the P-type layer surface.
3. The method of manufacturing a deep trench FET of claim 1, wherein the depth of the gate trench is 1.5 μm to 12 μm, the distance between the bottom of the gate trench and the N-type substrate is 0.1 μm to 0.6 μm, and the width of the gate trench is 0.8 μm to 6 μm.
4. The method of manufacturing a deep trench FET of claim 1, wherein the N-type source region extends from a bottom surface and a portion of a side surface of the gate trench into the N-type substrate, the N-type source region is formed by implanting N-type ions into a bottom of the gate trench to invert at least a P-type layer under the gate trench into the N-type source region, the N-type ions are phosphorus or arsenic, the ion implantation energy is 20kev to 800kev, and the ion implantation dose is 1e12cm -2 ~1e16cm -2 .
5. The method of manufacturing a deep trench field effect transistor of claim 1, wherein the deep trench field effect transistor is formed by a metal oxide semiconductor.
6. The method of manufacturing a deep trench FET of claim 1, wherein the gate oxide layer has a thickness of 100-1200A, the thick oxide layer has a thickness of 700-2000A, and the top surface of the first polysilicon layer is 0.1-1 μm higher than the interface between the N-type layer and the P-type layer.
7. The method of claim 1, further comprising performing a third ion implantation process on the exposed N-type layer to form a highly doped region after etching the dielectric layer in the first region of the active region to form a drain contact region, wherein the implantation ions comprise arsenic or phosphorus, the implantation dose is 1e15cm -2 ~1e16cm -2 , and the implantation energy is 5kev to 100kev.
8. The method of manufacturing a deep trench FET of claim 1, wherein the gate contact and the termination contact extend to a depth of 0 μm to 0.5 μm of the first polysilicon layer.
9. The method of manufacturing a deep trench FET of claim 1, wherein the metal layer has a thickness of 0.5 μm to 10 μm and the top surfaces of the source, gate and drain are uniform.
10. The method of manufacturing a deep trench FET of claim 1, wherein the difference in height between the upper surface of the second polysilicon layer and the surface of the N-type layer is 0 μm to 0.2 μm.
11. A deep trench field effect transistor, wherein the deep trench field effect transistor comprises a termination region and an active region, the deep trench field effect transistor comprising: an N-type substrate in which a P-type layer and an N-type layer are formed by ion implantation; The gate trench and the terminal trench are respectively formed in the active region and the terminal region, penetrate through the N-type layer and extend into the P-type layer; An N-type source region formed below a portion of the gate trench, the N-type source region extending from a lower portion of the gate trench into the N-type substrate; A gate oxide layer formed in the gate trench and the termination trench; The gate stack structure is formed in the gate groove and the terminal groove, and comprises a first polysilicon layer, a thick oxide layer and a second polysilicon layer, wherein the thick oxide layer is also formed on the side wall between the second polysilicon layer and the gate groove as well as between the second polysilicon layer and the terminal groove, the first polysilicon layer is positioned at the bottom of the terminal groove, the top surface of the first polysilicon layer is higher than the interface between the N-type layer and the P-type layer, and the second polysilicon layer is positioned at the top of the terminal groove; The dielectric layer is formed on the N-type layer; the source contact area is formed by etching the dielectric layer, the N-type layer, the P-type layer and the N-type substrate of the terminal area; A drain contact region formed by etching the dielectric layer in the second region of the active region, the drain contact region exposing the N-type layer; the gate contact region and the terminal contact region are formed by etching the dielectric layer and the gate stack structure of the second region of the active region and the terminal trench region of the terminal region, the gate contact region and the terminal contact region penetrate through the second polysilicon layer and the thick oxide layer and extend into the first polysilicon layer, and the source contact region is positioned at one side of the terminal contact region far away from the gate trench; the source electrode, the grid electrode and the drain electrode are respectively formed in the terminal contact area, the source contact area, the grid contact area and the drain contact area, and the source electrode is simultaneously connected with the terminal contact area and the source contact area.
12. The deep trench FET of claim 11, wherein the N-type substrate has a resistivity of 1-100 ohm cm and a thickness of 1.5-10 μm, the P-type layer has an implant ion comprising boron at an implant dose of 1e12cm -2 ~1e14cm -2 and an implant energy of 300-2000 kev, and the N-type layer has an implant ion comprising phosphorus at an implant dose of 1e12cm -2 ~1e14cm -2 and an implant energy of 200-500 kev.
13. The deep trench FET of claim 11, wherein the gate oxide layer has a thickness of 100-1200A, the thick oxide layer has a thickness of 700-2000A, and the top surface of the first polysilicon layer is 0.1-1 μm higher than the interface of the N-type layer and the P-type layer.
14. The deep trench FET of claim 11, wherein the source, gate and drain have a thickness of 0.5 μm to 10 μm and the top surfaces of the source, gate and drain are uniform in height.
15. The deep trench FET of claim 11 wherein said N-type layer below said drain contact region further comprises a highly doped region, wherein the implanted ions in said highly doped region comprise arsenic or phosphorous at a dose of 1e15cm -2 ~1e16cm -2 and an implantation energy of 5kev to 100kev.

Description

Deep trench field effect transistor and preparation method thereof Technical Field The invention belongs to the field of semiconductor integrated circuit design and manufacture, and particularly relates to a deep trench field effect transistor and a preparation method thereof. Background In conventional vertical power MOSFET structures, the Drain (Drain) is typically fabricated on the back side of a semiconductor wafer, and the Source (Source) and Gate (Gate) are fabricated on the front side of the wafer. Although the structure is mature, the structure has the limitations in the application scene of high frequency and high power density that 1) a single drain electrode heat dissipation mode on the back side cannot meet the heat dissipation requirement of high power density application, 2) a source electrode is required to be led out through wire bonding, and the wire bonding of the source electrode can lead in larger parasitic inductance, so that serious voltage overshoot and switching loss are generated in the switching process. To overcome the above problems, the industry has proposed a Source-Down (Source-Down) packaging technique. One key implementation way is to locate the source, gate and drain electrodes on the same plane, so as to facilitate package interconnection and heat dissipation. However, how to realize the extraction of each electrode of the device inside the device structure and ensure the feasibility and reliability of manufacturing without sacrificing the electrical performance (such as on-resistance and breakdown voltage) of the device is a challenge faced by the current technology. It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present application and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the application section. Disclosure of Invention In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a deep trench field effect transistor and a method for manufacturing the same, which are used for solving the problem that in the prior art, the extraction of each electrode inside the device structure is difficult to be realized without sacrificing the electrical performance of the device in the source-down packaging method. In order to achieve the above and other related objects, the present invention provides a method for manufacturing a deep trench field effect transistor, the deep trench field effect transistor including a termination region and an active region, the method comprising providing an N-type substrate, forming a P-type layer on a surface layer of the N-type substrate by a first ion implantation process, and forming an N-type layer on a surface layer of the P-type layer by a second ion implantation process; etching to form a gate trench and a termination trench in the active region and the termination region respectively, the gate trench and the termination trench penetrating the N-type layer and extending into the P-type layer, forming a barrier layer in the gate trench to shield the P-type layer of the gate contact region, forming an N-type source region in the gate trench by ion implantation, the N-type source region extending from the lower portion of the gate trench into the N-type substrate, removing the barrier layer, forming a gate oxide layer in the gate trench and the termination trench, forming a gate stack structure of a first polysilicon layer, a thick oxide layer and a second polysilicon layer in the gate trench and the termination trench, the thick oxide layer also forming a sidewall between the second polysilicon layer and the gate trench, the termination trench, depositing a dielectric layer on the N-type layer, etching to remove the dielectric layer in a first region of the active region to form a drain contact region, the drain contact region exposing the N-type layer, etching to form a polysilicon stack structure in the gate trench and the termination region and the second polysilicon layer, etching to form a polysilicon stack structure in the gate trench and the termination region, and etching to form a polysilicon stack structure in the gate contact region and the termination region and the polysilicon layer, and depositing a metal layer on the dielectric layer and in the terminal contact region, the source contact region, the gate contact region and the drain contact region, and patterning the metal layer to form a source electrode, a gate electrode and a drain electrode respectively, wherein the source electrode is simultaneously connected with the terminal contact region and the source contact region. Optionally, the resistivity of the N-type substrate is 1 ohm-cm to 100 ohm-cm, the thickness is