CN-121257432-B - Clock structure description method, device, electronic equipment and storage medium

CN121257432BCN 121257432 BCN121257432 BCN 121257432BCN-121257432-B

Abstract

The invention provides a clock structure description method, a device, electronic equipment and a storage medium, which relate to the technical field of structure description and comprise the steps of obtaining clock structure description information, wherein the clock structure description information is organized in a key value pair form, and the key value pair comprises an identification key and an attribute key; analyzing the key value pair, extracting the clock structure element, constructing a clock structure model based on the hierarchical relationship of the key value pair, and generating a clock structure description file or verification information based on the clock structure model. In the mode, the clock has an intuitive clock structure, and is convenient for describing the flexible clock structure and adding a new clock structure.

Inventors

ZHOU XINLAI
JIA SHUYUN
HAO ZHIKUN
LIU LEZHI
WANG YAO

Assignees

翼华科技(北京)有限公司

Dates

Publication Date: 20260508
Application Date: 20250928

Claims (8)

1. A method of describing a clock structure, the method comprising: Acquiring clock structure description information, wherein the clock structure description information is organized in the form of key value pairs, and the key value pairs comprise an identification key and an attribute key; The method comprises the steps of analyzing the key value pair, extracting clock structure elements, identifying the identification key to determine the start of a new description structure, reading at least one attribute key associated with the identification key and the corresponding value of the attribute key, and identifying a common key, a PLL key, a clock tree key or a special key in the key value pair according to the description structure key to determine the type of the described clock structure; The clock structure model is built based on the hierarchical relation of the key value pairs, and comprises the steps of analyzing the retraction amount of the key value pairs, determining a first key value pair as a first level structure, determining a second key value pair as a second level structure, wherein the second level structure is a sub-level structure belonging to the first level structure, the second key value pair is a key value pair with the retraction amount larger than the first key value pair and smaller than a third key value pair, and the third key value pair is a sub-level structure belonging to the second level structure; and generating a clock structure description file or verification information based on the clock structure model.
2. The method of claim 1, wherein the special key comprises at least one of a VLOG key, a DMARK key, and a PORT key.
3. The method according to claim 2, wherein the method further comprises: when the VLOG key is identified, extracting a Verilog code from the value of the VLOG key, and embedding the Verilog code into the generated description file; when the DMARK key is identified, setting an identification for a DFT flow in the clock structure model based on the value of the DMARK key; defining an input/output PORT of a module based on a value of the PORT key when the PORT key is recognized; The input-output port is associated with an internal signal defined by the VLOG key.
4. The method of claim 1, wherein generating a clock structure description file based on the clock structure model comprises: and generating at least one of RTL codes, SDC constraint files or clock structure diagrams based on the clock structure model.
5. The method of claim 1, wherein generating verification information based on the clock structure model comprises: Generating clock connection information for programming a test program based on the connection relation in the clock structure model; And/or outputting the SOC clock structure diagram for the middle-back end process.
6. A clock structure description apparatus for implementing the clock structure description method of any one of claims 1 to 5, the apparatus comprising: the clock structure description information acquisition module is used for acquiring clock structure description information, wherein the clock structure description information is organized in a key value pair form, and the key value pair comprises an identification key and an attribute key; the key value pair analyzing module is used for analyzing the key value pair and extracting clock structure elements; the clock structure model construction module is used for constructing a clock structure model based on the hierarchical relationship of the key value pairs; and the clock structure description module is used for generating a clock structure description file or verification information based on the clock structure model.
7. An electronic device comprising a processor and a memory, the memory storing computer-executable instructions executable by the processor, the processor executing the computer-executable instructions to implement the clock structure description method of any one of claims 1 to 5.
8. A computer readable storage medium storing computer executable instructions which, when invoked and executed by a processor, cause the processor to implement the clock structure description method of any one of claims 1 to 5.

Description

Clock structure description method, device, electronic equipment and storage medium Technical Field The present invention relates to the field of structure description technologies, and in particular, to a clock structure description method, a clock structure description device, an electronic device, and a storage medium. Background At present, an automatic method is mostly adopted in chip design to generate a clock circuit, and a clock structure needs to be described first. The description mode provided in the related art is relatively fixed, and meanwhile, the clock structure is not visual, so that flexible clock structure description and new clock structure addition are inconvenient. Disclosure of Invention In view of the above, the present invention is directed to a clock structure description method, apparatus, electronic device and storage medium, which have intuitive clock structures, facilitate the description of flexible clock structures and add new clock structures. In a first aspect, an embodiment of the present invention provides a clock structure description method, including obtaining clock structure description information, where the clock structure description information is organized in a key-value pair, where the key-value pair includes an identifier key and an attribute key, analyzing the key-value pair, extracting a clock structure element, constructing a clock structure model based on a hierarchical relationship of the key-value pair, and generating a clock structure description file or verification information based on the clock structure model. In a preferred embodiment of the present invention, the parsing key-value pair includes identifying an identifier key to determine a start of a new description structure, reading at least one attribute key associated with the identifier key and a corresponding value of the attribute key, and identifying a common key, PLL key, clock tree key or special key in the key-value pair according to the description structure key to determine a type of the described clock structure. In a preferred embodiment of the present invention, the special key includes at least one of a VLOG key, a DMARK key, and a PORT key. In a preferred embodiment of the present invention, the method further includes extracting a Verilog code from the value of the VLOG key and embedding the Verilog code into the generated description file when the VLOG key is identified, setting an identification for the DFT process in the clock structure model based on the value of the DMARK key when the DMARK key is identified, defining an input/output PORT of the module based on the value of the PORT key when the PORT key is identified, and associating the input/output PORT with the internal signal defined by the VLOG key. In a preferred embodiment of the invention, the clock structure model is constructed based on the hierarchical relationship of key value pairs, and the clock structure model comprises analyzing the indentation amount of the key value pairs, determining the first key value pair as a first level structure, determining the first key value pair as a key value pair with the minimum indentation amount, determining the second key value pair as a second level structure, wherein the second level structure is a sub-level structure belonging to the first level structure, the second key value pair is a key value pair with the indentation amount larger than the first key value pair and smaller than the third key value pair, and the third key value pair is a sub-level structure belonging to the second level structure. In a preferred embodiment of the present invention, the generating the clock structure description file based on the clock structure model includes generating at least one of an RTL code, an SDC constraint file, or a clock structure diagram based on the clock structure model. In the preferred embodiment of the invention, the verification information is generated based on the clock structure model, and the verification information comprises clock connection information used for programming the test program and/or SOC clock structure diagram used for the middle-back end flow is output based on the connection relation in the clock structure model. In a second aspect, the embodiment of the invention also provides a clock structure description device, which comprises a clock structure description information acquisition module, a clock structure description information generation module and a clock structure description module, wherein the clock structure description information acquisition module is used for acquiring clock structure description information, the clock structure description information is organized in a key value pair form, the key value pair comprises an identification key and an attribute key, the key value pair analysis module is used for analyzing the key value pair to extract clock structure elements, the clock structure model construction module is used for