CN-121279234-B - Gradient descent-based integrated clock gate layout method, apparatus, device and storage medium

CN121279234BCN 121279234 BCN121279234 BCN 121279234BCN-121279234-B

Abstract

The disclosure provides an integrated clock gate layout method, device, equipment and storage medium based on gradient descent, wherein the method comprises the steps of determining an anchor point of an integrated clock gate based on a register position of a register controlled by the integrated clock gate; the method comprises the steps of determining a corresponding line length loss function based on a first distance between an integrated clock gate and an anchor point and a second distance between the integrated clock gate and a register, determining a total loss function based on the line length loss function and a layout loss function, updating the position of the integrated clock gate based on the gradient descent direction of the total loss function to obtain a layout position enabling the total loss function to meet a convergence condition, wherein the first weight of the first distance is larger than the second weight of the second distance. The multi-dimensional improvement of the layout quality can be realized while the performance of the clock tree is ensured.

Inventors

ZHANG JIUXIN
DING WEIBIN
ZHANG XINCHENG
ZHOU FEI

Assignees

芯行纪科技有限公司

Dates

Publication Date: 20260505
Application Date: 20251208

Claims (10)

1. An integrated clock gate layout method based on gradient descent, comprising: determining an anchor point of the integrated clock gate based on a register position of a register controlled by the integrated clock gate, wherein the anchor point is updated based on a last iteration position, a current real-time position and a smoothing coefficient of the register; determining a corresponding line length loss function based on a first distance between the integrated clock gate and the anchor point and a second distance between the integrated clock gate and the register, wherein a first weight of the first distance is greater than a second weight of the second distance; Determining a total loss function based on the line length loss function and a layout loss function, the layout loss function including at least one of a density loss function, a congestion loss function, or a timing loss function; And updating the position of the integrated clock gate based on the gradient descent direction of the total loss function to obtain a layout position for enabling the total loss function to meet a convergence condition.
2. The method as recited in claim 1, further comprising: And in response to detecting that the position change of the register is greater than a preset change threshold, or the number of iterations is greater than a preset number, updating the anchor point based on the current real-time position of the register.
3. The method of claim 1, wherein the density loss function is determined based on a number of elements per unit area or an area ratio; The congestion loss function is determined based on the occupation of wiring resources and/or the remaining routable space; the timing penalty function is determined based on the propagation delay of the clock signal, and the setup time and hold time of the register.
4. The method of claim 1, wherein updating the position of the integrated clock gate based on the gradient descent direction of the total loss function comprises: Partial derivatives of the position coordinates of the total loss function about the integrated clock gate are obtained, and gradient vectors are obtained; And updating the position of the integrated clock gate according to the gradient vector and the learning rate.
5. The method of claim 4, wherein the convergence condition comprises at least one of: in response to detecting that the change in the total loss function is less than a preset convergence threshold, the number of iterations reaches an upper limit, or the modulus of the gradient vector is less than a preset value.
6. The method of claim 1, wherein determining the corresponding line length penalty function based on a first distance between the integrated clock gate and the anchor point and a second distance between the integrated clock gate and the register comprises: And carrying out weighted summation based on the first distance and the first weight and the second distance and the second weight to obtain the line length loss function.
7. The method of claim 1, wherein determining an anchor point for the integrated clock gate based on a register location of a register controlled by the integrated clock gate comprises: And determining the anchor point by adopting a violent movement method based on the register position, wherein the violent movement method further comprises the steps of determining the anchor point based on the centroid of the register position or determining the anchor point by carrying out weighted average based on the register position and the corresponding position weight.
8. An integrated clock gate layout apparatus based on gradient descent, comprising: The anchor point module is used for determining an anchor point of the integrated clock gate based on the register position of the register controlled by the integrated clock gate, wherein the anchor point is updated based on the last iteration position, the current real-time position and the smoothing coefficient of the register; A penalty function module configured to determine a corresponding line length penalty function based on a first distance between the integrated clock gate and the anchor point and a second distance between the integrated clock gate and the register, the first weight of the first distance being greater than the second weight of the second distance, and determine a total penalty function based on the line length penalty function and a layout penalty function, the layout penalty function including at least one of a density penalty function, a congestion penalty function, or a timing penalty function; And the position updating module is used for updating the position of the integrated clock gate based on the gradient descending direction of the total loss function to obtain a layout position for enabling the total loss function to meet a convergence condition.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method of any one of claims 1 to 7 when the program is executed.
10. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1 to 7.

Description

Gradient descent-based integrated clock gate layout method, apparatus, device and storage medium Technical Field The disclosure relates to the field of chip layout, and in particular relates to an integrated clock gate layout method, device, equipment and storage medium based on gradient descent. Background In the digital back-end layout, the method for integrating the clock gate layout mainly comprises the steps of carrying out violent movement for a plurality of times, selecting a plurality of time points in a plurality of iterations of the layout process, calculating the expected position of the integrated clock gate through the position coordinates of a register driven by the integrated clock gate, and then directly moving the integrated clock gate to the position. However, this approach has a number of problems, firstly, the target location of the integrated clock gate movement calculated by the control register coordinates is not necessarily a legal layout location, possibly on the module, a layout blockage, and possibly even outside the chip layout-able area. Additional algorithms are required to move it to a placeable location, often a distance from the desired location. Second, the target locations for multiple integrated clock gate movements may be very close, resulting in excessive local layout density and routing congestion. The target location becomes more severely after movement if the local density and winding congestion were already large. Third, the analytical layout solver typically solves for the layout position optimal solution by gradient descent. Multiple violent movements can lead to spatial variations in solution, and convergence becomes more difficult. Disclosure of Invention Accordingly, an object of the present disclosure is to provide an integrated clock gate layout method, system, device and storage medium based on gradient descent, so as to solve the technical problems of low layout efficiency and quality of the integrated clock gate layout. In a first aspect of the present disclosure, an integrated clock gate layout method based on gradient descent is provided, including: Determining an anchor point of the integrated clock gate based on a register location of a register controlled by the integrated clock gate; determining a corresponding line length loss function based on a first distance between the integrated clock gate and the anchor point and a second distance between the integrated clock gate and the register, wherein a first weight of the first distance is greater than a second weight of the second distance; Determining a total loss function based on the line length loss function and a layout loss function, the layout loss function including at least one of a density loss function, a congestion loss function, or a timing loss function; And updating the position of the integrated clock gate based on the gradient descent direction of the total loss function to obtain a layout position for enabling the total loss function to meet a convergence condition. In a second aspect of the present disclosure, an integrated clock gate layout apparatus based on gradient descent is provided, comprising: an anchor point module, configured to determine an anchor point of the integrated clock gate based on a register position of a register controlled by the integrated clock gate; A penalty function module configured to determine a corresponding line length penalty function based on a first distance between the integrated clock gate and the anchor point and a second distance between the integrated clock gate and the register, the first weight of the first distance being greater than the second weight of the second distance, and determine a total penalty function based on the line length penalty function and a layout penalty function, the layout penalty function including at least one of a density penalty function, a congestion penalty function, or a timing penalty function; And the position updating module is used for updating the position of the integrated clock gate based on the gradient descending direction of the total loss function to obtain a layout position for enabling the total loss function to meet a convergence condition. In a third aspect of the present disclosure, there is provided an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method according to the first aspect when executing the program. In a fourth aspect of the present disclosure, there is provided a non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of the first aspect. As can be seen from the foregoing, the present disclosure provides an integrated clock gate layout method, system, apparatus and storage medium based on gradient descent. Determining an anchor point through the position of a register controlled by the integrated clock gat