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CN-121281574-B - Reluctance weight storage circuit, architecture, pulse neural network magnetic computing acceleration chip system and electronic equipment

CN121281574BCN 121281574 BCN121281574 BCN 121281574BCN-121281574-B

Abstract

The application provides a reluctance weight storage circuit, a framework, a pulse neural network magnetic computing acceleration chip system and electronic equipment, wherein the reluctance weight storage circuit is used for storing weight values of the reluctance weight storage framework, the reluctance weight storage circuit comprises a plurality of weight units which are fully connected in a matrix form, each weight unit comprises a plurality of groups of complementary voltage control magnetic anisotropic magnetic tunnel junction devices, each group of complementary voltage control magnetic anisotropic magnetic tunnel junction devices comprises two magnetic tunnel junction elements with opposite reluctance states, the plurality of groups of complementary voltage control magnetic anisotropic magnetic tunnel junction devices are connected in series, the reluctance weight storage circuit adopts a serial voltage division topological structure, and generates linear reference voltages by utilizing resistance state differences of the complementary voltage control magnetic anisotropic magnetic tunnel junction devices, so that signal sampling margin is remarkably improved, and meanwhile process sensitivity is reduced.

Inventors

  • XU YUAN

Assignees

  • 寒序科技(北京)有限公司

Dates

Publication Date
20260512
Application Date
20251010

Claims (10)

  1. 1. A magneto-resistive weight storage circuit, wherein the magneto-resistive weight storage circuit is configured to store a weight value of a magneto-resistive weight storage architecture; the magneto-resistance weight storage circuit comprises a plurality of weight units, wherein the weight units are fully connected in a matrix form; Each weight unit comprises a plurality of groups of complementary voltage control magnetic anisotropic magnetic tunnel junction devices, wherein each group of complementary voltage control magnetic anisotropic magnetic tunnel junction devices comprises two magnetic tunnel junction elements with opposite magnetic resistance states; After the magnetic tunnel junction elements with the same magnetic resistance state in each group of voltage control magnetic anisotropic magnetic tunnel junction devices are connected in series, the magnetic tunnel junction elements with opposite magnetic resistance states are connected in series.
  2. 2. The magnetoresistive weight memory circuit of claim 1 wherein the weight cell implements N different weight values through different resistance states of 2 x (N-1) of the voltage controlled magnetically anisotropic magnetic tunnel junction devices, where N is an integer greater than 1; when the corresponding coding value of the voltage control magnetic anisotropic magnetic tunnel junction device is 0, a low resistance state is represented; and when the corresponding coding value of the voltage control magnetic anisotropic magnetic tunnel junction device is 1, the high resistance state is represented.
  3. 3. The magnetoresistive weight memory circuit of claim 1 wherein the mapping of the weight value of the weight cell to the magnetoresistive state of the voltage-controlled magnetically anisotropic magnetic tunnel junction device is: different weight values are realized by controlling the combination of the low resistance state and the high configuration of the magnetic anisotropic magnetic tunnel junction device through different voltages; when all voltage control magnetic anisotropic magnetic tunnel junction devices in a pull-up network of the weight unit are in a low resistance state, the weight unit corresponds to the largest weight value; All voltage control magnetic anisotropic magnetic tunnel junction devices in the pull-up network of the weight unit are in a high resistance state, and when all voltage control magnetic anisotropic magnetic tunnel junction devices in the pull-down network of the weight unit are in a low resistance state, the weight unit corresponds to a minimum weight value.
  4. 4. A magneto-resistive weight storage architecture comprising the magneto-resistive weight storage circuit of any one of claims 1-3, an integral-leakage-firing neuron module, and a voltage-controlled current source array; The output of each column of weight units is connected to one integral-leakage-ignition neuron; Triggering the corresponding weight unit to output a reference voltage by an input pulse; the voltage-controlled current source array converts the reference voltage into charging current and drives membrane potential integration of the integral-leakage-ignition neuron; when the membrane potential exceeds a threshold, the magneto-resistive weight storage architecture outputs a pulse and resets the integral-leakage-firing neurons.
  5. 5. The magnetoresistive weight memory architecture of claim 4, wherein, The magneto-resistance weight storage architecture asynchronously responds to an input pulse signal; the weight unit is activated only when triggered by an input pulse; the magneto-resistive weight storage architecture is devoid of global clock signals.
  6. 6. The magnetoresistive weight-storing architecture of claim 4, wherein the integrate-leak-fire neuron comprises: an integration capacitor for accumulating an input current and forming a film potential; the leakage resistor is connected with the integrating capacitor in parallel to realize membrane potential attenuation; A comparator circuit that triggers an output pulse when the membrane potential exceeds a threshold value; And a reset circuit that resets the film potential after outputting the pulse.
  7. 7. The multilayer magneto-resistance weight storage architecture is characterized by comprising an input layer, a hidden layer and an output layer; the input layer is used for receiving the preprocessed pulse signals; Each layer of the hidden layer includes a plurality of integral-leakage-firing neurons, the number of integral-leakage-firing neurons being determined from the volume of the multilayer magnetoresistive weight-storage architecture and the identification accuracy of the multilayer magnetoresistive weight-storage architecture; the output layer is used for outputting the identification result of the multi-layer magnetic resistance weight storage architecture; a magneto-resistive weight storage circuit as claimed in any one of claims 1 to 3 for each layer of integrating-leakage-firing neurons.
  8. 8. The multi-layered magnetoresistive weight memory architecture of claim 7 wherein the input layer, the hidden layer, and the output layer are triggered by a pulse signal without clock synchronization.
  9. 9. A pulse neural network magnetic computing acceleration chip system, characterized by comprising the multilayer magneto-resistance weight storage architecture according to any one of claims 7-8, wherein the pulse neural network magnetic computing acceleration chip system is used for realizing biological nerve bionics or recognition according to the multilayer magneto-resistance weight storage architecture.
  10. 10. An electronic device, characterized by comprising a multi-layer magneto-resistive weight storage architecture according to any of claims 7-8, said electronic device being configured to implement bio-neuro-bionics or recognition according to said multi-layer magneto-resistive weight storage architecture.

Description

Reluctance weight storage circuit, architecture, pulse neural network magnetic computing acceleration chip system and electronic equipment Technical Field The application relates to the technical field of circuits, in particular to a magnetic resistance weight storage circuit, a magnetic resistance weight storage architecture, a pulse neural network magnetic computing acceleration chip system and electronic equipment. Background Neuromorphic computation is a computational paradigm inspired by biological nervous systems, with the core of a dynamic information processing mechanism that simulates neurons and synapses, breaking through the bottlenecks of traditional computing architecture through asynchronous event-driven, space-time coding, and energy efficiency optimization. Compared with the traditional von neumann architecture, the neuromorphic computing system can remarkably reduce power consumption and improve computing efficiency, and is particularly suitable for application scenes with strict requirements on energy efficiency, such as edge computing, internet of things and real-time signal processing. In the deep learning field, traditional artificial neural networks (ARTIFICIAL NEURAL NETWORK, ANN) rely on continuous real operations, employ activation functions (e.g., reLU, ELU, etc.) to perform nonlinear transformations, and train through back propagation algorithms. However, the manner in which ANN is calculated varies significantly from the biological nervous system, resulting in challenges in terms of energy efficiency and real-time. In contrast, the magneto-resistive weight storage architecture (Spiking Neural Network, SNN) is used as a third generation neural network model, is closer to the operation mechanism of biological neurons, and has higher biological interpretability and calculation efficiency. The core features of SNN are its neuron model and information coding scheme. Specifically, SNN uses a leak-integrate-Fire (LEAKY INTEGRATE-and-Fire, LIF) model to simulate the dynamic behavior of biological neurons, where the neurons generate discrete pulse signals through the accumulation of membrane potential and threshold triggering mechanisms. The space-time coding mode based on the events enables the SNN to transmit information in a sparse pulse sequence, so that the calculation and communication overhead is greatly reduced. While SNNs have advantages in terms of energy efficiency and biological rationality, their hardware implementation still faces several challenges, including: The pulse dynamic characteristic of SNN causes the calculation process to be more complex than ANN, and the traditional calculation architecture is difficult to support with high efficiency; the training difficulty is high, because of the discreteness of the pulse signals, the SNN training algorithm is difficult to directly apply back propagation, and the performance of the SNN training algorithm in complex tasks is limited; the occupation of hardware resources is high, the existing neuromorphic chip generally needs a special circuit design, and SNN models with different scales are difficult to flexibly adapt. Therefore, there is a need for an efficient and scalable neuromorphic computing architecture that can improve the computational performance and training efficiency of SNN while guaranteeing low power consumption, so as to meet the requirements of edge intelligence and real-time signal processing. Disclosure of Invention In view of the foregoing, in a first aspect, embodiments of the present application provide a magneto-resistive weight storage circuit for storing weight values of a magneto-resistive weight storage architecture; the magneto-resistance weight storage circuit comprises a plurality of weight units, wherein the weight units are fully connected in a matrix form; Each weight unit comprises a plurality of groups of complementary voltage control magnetic anisotropic magnetic tunnel junction devices, wherein each group of complementary voltage control magnetic anisotropic magnetic tunnel junction devices comprises two magnetic tunnel junction elements with opposite magnetic resistance states; The plurality of sets of complementary voltage controlled magnetic anisotropic magnetic tunnel junction devices are connected in series. Optionally, the weight unit realizes N different weight values through different resistance states of 2 x (N-1) of the voltage controlled magnetic anisotropic magnetic tunnel junction devices; when the corresponding coding value of the voltage control magnetic anisotropic magnetic tunnel junction device is 0, a low resistance state is represented; and when the corresponding coding value of the voltage control magnetic anisotropic magnetic tunnel junction device is 1, the high resistance state is represented. Optionally, the mapping relationship between the weight value of the weight unit and the magnetic resistance state of the voltage control magnetic anisotropic magnetic tunnel j