CN-121308732-B - Power-on reset circuit based on resistance voltage division type detection

Abstract

The invention discloses a power-on reset circuit based on resistance voltage division detection, which comprises a first detection unit, a second detection unit and a logic comparison unit, wherein the first detection unit detects an input first bias signal to obtain a first detection voltage, the second detection unit detects an input second bias signal to obtain a second detection voltage, the logic comparison unit comprises a NAND gate, a first input end of the NAND gate is connected with the first detection unit, a second input end of the NAND gate is connected with the second detection unit, and the NAND gate outputs a corresponding reset signal according to the first detection voltage and the second detection voltage, so that the power-on speed is high, and the whole circuit area is reduced.

Inventors

• BAI LIXIA
• ZHAO GUANGWEI
• LI WENMING
• LIU MEIDONG
• PAN TIANLONG
• YIN JIAYU
• ZHENG ZHEXIN
• Hong Hezuo

Assignees

• 厦门半导体工业技术研发有限公司

Dates

Publication Date

20260505

Application Date

20251211

Claims (6)

1. 1. A power-on reset circuit based on resistance voltage division type detection is characterized by comprising: the first detection unit detects the input first bias signal to obtain a first detection voltage; the second detection unit is used for detecting the input second bias signal to obtain a second detection voltage; The logic comparison unit comprises a NAND gate, a first input end of the NAND gate is connected with the first detection unit, a second input end of the NAND gate is connected with the second detection unit, and the NAND gate outputs a corresponding reset signal according to the first detection voltage and the second detection voltage; wherein the first detection unit includes: The first resistor voltage division unit is used for carrying out voltage division sampling on an input power supply to obtain a first initial detection voltage; The first starting control unit is connected with the first resistor voltage dividing unit so as to conduct according to the first initial detection voltage; the first charging and discharging unit is connected with the first starting control unit, and the first charging and discharging unit obtains a corresponding first detection voltage according to the first bias signal after the first starting control unit is conducted; wherein the first resistive voltage dividing unit includes: one end of the first resistor is grounded; One end of the second resistor is connected with the other end of the first resistor, and the other end of the second resistor is connected to a power supply; wherein the first start control unit includes: one end of the first capacitor is connected between the first resistor and the second resistor, and the other end of the first capacitor is grounded; The grid electrode of the first MOS tube is connected between the first resistor and the second resistor, and the source electrode of the first MOS tube is connected to the ground; Wherein the first charge and discharge unit includes: the grid electrode of the second MOS tube is connected to the starting and biasing circuit generator unit so as to receive a first biasing signal, the source electrode of the second MOS tube is connected to a power supply, and the drain electrode of the second MOS tube is connected to the drain electrode of the first MOS tube; And one end of the second capacitor is connected with the power supply, and the other end of the second capacitor is connected between the drain electrode of the second MOS tube and the drain electrode of the first MOS tube.
2. 2. The power-on reset circuit based on resistive voltage division detection of claim 1, wherein the second detection unit comprises: The second resistor voltage division unit is used for carrying out voltage division sampling on an input power supply to obtain a second initial detection voltage; the second starting control unit is connected with the second resistor voltage dividing unit so as to conduct according to the second initial detection voltage; and the second charging and discharging unit is connected with the second starting control unit, and the second charging and discharging unit obtains a corresponding second detection voltage according to the second bias signal after the second starting control unit is conducted.
3. 3. The power-on reset circuit based on resistive voltage division detection of claim 2, wherein the second resistive voltage division unit comprises: The one end of the third resistor is grounded; And one end of the fourth resistor is connected with the other end of the third resistor, and the other end of the fourth resistor is connected to a power supply.
4. 4. The power-on reset circuit based on resistive voltage division detection of claim 3, wherein the second start-up control unit comprises: A third capacitor, one end of which is connected between the third resistor and the fourth resistor, and the other end of which is connected to a power supply; And the grid electrode of the third MOS tube is connected between the third resistor and the fourth resistor, and the source electrode of the third MOS tube is connected to a power supply.
5. 5. The power-on reset circuit based on resistive voltage division detection of claim 4, wherein the second charge-discharge unit comprises: A grid electrode of the fourth MOS tube is connected to the starting and biasing circuit generator unit so as to receive a second biasing signal, a source electrode of the fourth MOS tube is connected to the ground, and a drain electrode of the fourth MOS tube is connected to a drain electrode of the third MOS tube; And one end of the fourth capacitor is connected to the ground, and the other end of the fourth capacitor is connected between the drain electrode of the fourth MOS tube and the drain electrode of the third MOS tube.
6. 6. The power-on reset circuit based on resistance voltage division detection according to claim 1, wherein the logic comparison unit further comprises a first inverter, a second inverter and a third inverter, an input end of the first inverter is connected with an output end of the first detection unit, an output end of the first inverter is connected with a first input end of the nand gate, an input end of the second inverter is connected with an output end of the second detection unit, an output end of the second inverter is connected with an input end of the third inverter, and an output end of the third inverter is connected with a second input end of the nand gate.

Description

Power-on reset circuit based on resistance voltage division type detection Technical Field The invention relates to the technical field of reset circuits, in particular to a power-on reset circuit based on resistance voltage division type detection. Background IN the related art, IN the power-on process of the existing power-on reset circuit, pbias and Nbias start-up are required to wait, after the circuit is started, a comparator COMP is adopted to compare the voltages and output results are used as power-on reset signals, the scheme needs strict time sequence control between the circuit starting time (the stable time sequence of the PBIAS and NBIA voltages) and the detection sampling time (the stable speed of R1 and R2) of the voltages IP and IN, otherwise, the output result of the comparator is wrong, POR power-on fails, and IN addition, the offset of the comparator itself can cause the time sequence control of the whole circuit to be difficult, so that the circuit implementation is complex. Disclosure of Invention The present invention aims to solve at least to some extent one of the technical problems in the above-described technology. Therefore, an object of the present invention is to provide a power-on reset circuit based on resistance voltage division detection, wherein voltage detection is performed through resistance voltage division, and a nand logic gate replaces a comparator as a detection result, so that the power-on speed is high, and the overall circuit area is reduced. In order to achieve the above purpose, the power-on reset circuit based on resistance voltage division detection provided by the embodiment of the invention comprises a first detection unit, a second detection unit and a logic comparison unit, wherein the first detection unit detects an input first bias signal to obtain a first detection voltage, the second detection unit detects an input second bias signal to obtain a second detection voltage, the logic comparison unit comprises a NAND gate, a first input end of the NAND gate is connected with the first detection unit, a second input end of the NAND gate is connected with the second detection unit, and the NAND gate outputs a corresponding reset signal according to the first detection voltage and the second detection voltage, so that the power-on speed is high, and the whole circuit area is reduced. In addition, the power-on reset circuit based on resistance voltage division type detection provided by the embodiment of the invention can also have the following additional technical characteristics: Optionally, the first detection unit comprises a first resistor voltage division unit, a first starting control unit and a first charging and discharging unit, wherein the first resistor voltage division unit divides and samples an input power supply to obtain a first initial detection voltage, the first starting control unit is connected with the first resistor voltage division unit to conduct according to the first initial detection voltage, the first charging and discharging unit is connected with the first starting control unit, and the first charging and discharging unit obtains a corresponding first detection voltage according to the first bias signal after the first starting control unit is conducted. Further, the first resistor voltage dividing unit comprises a first resistor, one end of the first resistor is grounded, and a second resistor, one end of the second resistor is connected with the other end of the first resistor, and the other end of the second resistor is connected to a power supply. Further, the first starting control unit comprises a first capacitor, a first MOS tube and a first MOS tube, wherein one end of the first capacitor is connected between the first resistor and the second resistor, the other end of the first capacitor is grounded, the grid electrode of the first MOS tube is connected between the first resistor and the second resistor, and the source electrode of the first MOS tube is connected to the ground. Further, the first charge-discharge unit comprises a second MOS tube, a second capacitor and a second capacitor, wherein a grid electrode of the second MOS tube is connected to the starting and bias circuit generator unit so as to receive a first bias signal, a source electrode of the second MOS tube is connected to a power supply, a drain electrode of the second MOS tube is connected to a drain electrode of the first MOS tube, one end of the second capacitor is connected with the power supply, and the other end of the second capacitor is connected between the drain electrode of the second MOS tube and the drain electrode of the first MOS tube. Optionally, the second detection unit comprises a second resistor voltage division unit, a second starting control unit and a second charging and discharging unit, wherein the second resistor voltage division unit divides and samples an input power supply to obtain a second initial detection voltage, the