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CN-121333472-B - Time synchronization device and communication equipment

CN121333472BCN 121333472 BCN121333472 BCN 121333472BCN-121333472-B

Abstract

The application discloses a time synchronization device and communication equipment, wherein a PTP sending module receives an Ethernet frame and outputs a first sending data packet start identification signal and a first sending signal, a time stamp processing module assigns a first current time stamp to a first sending time latch signal and assigns the first sending time latch signal to a time stamp t1 register, a processor acquires a time stamp t1 to be a synchronous message/a follow message to be stamped, a PCS receiving module receives and outputs the first receiving data packet start identification signal, the PTP receiving module analyzes a delay request message to output the first receiving data packet start identification signal, a time stamp processing module assigns a second current time stamp to the first receiving time latch signal and assigns the first receiving time latch signal to a time stamp t4 register, and the processor acquires the time stamp t4 to stamp a delay response message. The application can realize high-precision time synchronization.

Inventors

  • YUAN ZHUOLI
  • WANG JIAXIN
  • LI CHENYU

Assignees

  • 杭州来克莎科技有限公司

Dates

Publication Date
20260508
Application Date
20251211

Claims (8)

  1. 1. A time synchronization apparatus for a master clock node in a precision time protocol, PTP, domain, the PTP domain further comprising a slave clock node, the apparatus comprising a processor and an FPGA, the FPGA comprising: A time counter for generating a time stamp in real time; the PTP sending module is used for responding to the received first Ethernet frame output by the processor, outputting a first sending data packet start identification (SOP) signal, and responding to the analyzed synchronous message in the first Ethernet frame, outputting a first sending signal; the time stamp processing module comprises a time stamp t1 pulse register and a time stamp t1 register, and is used for assigning a first current time stamp acquired from the time counter to a first sending time latching signal in response to a first sending SOP signal and assigning the first sending time latching signal to the time stamp t1 register in response to the first sending signal; The processor is used for reading a first sending time latching signal from the time stamp t1 register as a time stamp t1, marking the time stamp t1 for the synchronous message/the following message, and outputting the first Ethernet frame to a slave clock node through the FPGA; The FPGA further comprises: The PCS receiving module is used for responding to the second Ethernet frame output from the clock node and outputting a first received data packet start identification SOP signal; the PTP receiving module is used for responding to and analyzing a delay request message in the second Ethernet frame to output a first receiving signal; The time stamp processing module is used for responding to a first receiving SOP signal, assigning a second current time stamp acquired from the time counter to a first receiving time latching signal, and assigning the first receiving time latching signal to a time stamp t4 register in response to the first receiving signal; The processor is used for reading the first receiving time latching signal from the time stamp t4 register as a time stamp t4, stamping the time stamp t4 on the delayed response message, and outputting a third Ethernet frame carrying the delayed response message to the slave clock node through the FPGA; wherein the processor configuration supports a two-step mode; when the PTP sending module analyzes the SOP identification of the first Ethernet frame, a first sending SOP signal is output; The time stamp processing module responds to the rising edge of the first sending SOP signal, obtains a first current time stamp from the time counter, and assigns the first current time stamp to a first sending time latching signal; the PTP sending module continues to analyze a synchronous message in a first Ethernet frame, responds to the MsgType field value in the synchronous message as 0, outputs a first sending signal, and outputs the first Ethernet frame to the slave clock node; the timestamp processing module responds to the rising edge of the first sending signal and assigns the first sending time latching signal to a first sending time marking signal; After the processor sends the synchronous message, setting a time stamp t1 pulse signal in a time stamp t1 pulse register to be 1; The time stamp processing module is used for responding to the rising edge of the time stamp t1 pulse signal and triggering the first sending time stamp signal to be latched into a time stamp t1 register; The processor reads a time stamp t1 register, takes a read first sending time stamp signal as a time stamp t1, marks the time stamp t1 on the following message, and outputs a fourth Ethernet frame carrying the following message to the slave clock node through the PTP sending module.
  2. 2. The time synchronization device of claim 1, wherein the processor configuration supports a single step mode, The PTP sending module outputs a first sending SOP signal when analyzing the SOP identification of the first Ethernet frame; The time stamp processing module responds to the rising edge of the first sending SOP signal, obtains a first current time stamp from the time counter, and assigns the first current time stamp to a first sending time latching signal; the PTP sending module continues to execute the analysis of the synchronous message in the first Ethernet frame, and responds to the MsgType field value in the synchronous message as 0 to output a first sending signal; The time stamp processing module responds to the rising edge of the first sending signal, assigns the first sending time latching signal to a first sending time marking signal and sends the first sending time latching signal to the PTP sending module; The PTP sending module obtains the byte position of OriginTimestamp fields in the synchronous message by using a byte counting mode, adds a time stamp t1 indicated by the first sending time stamp signal to the byte position, and outputs a first Ethernet frame carrying the synchronous message to the slave clock node.
  3. 3. The apparatus of claim 1, wherein the time stamp processing module comprises a time stamp t4 pulse register and a time stamp t4 register, The PCS receiving module outputs a first received data packet start identification SOP signal when analyzing the SOP identification in the second Ethernet frame; the time stamp processing module responds to the rising edge of the first receiving SOP signal and assigns a second current time stamp acquired from the time counter to a first receiving time latch signal; the PTP receiving module responds to the MsgType field value in the delay request message of the second Ethernet frame to be 0x01, outputs a first receiving signal and sends the delay request message to the processor; the timestamp processing module responds to the rising edge of the first receiving signal and assigns the first receiving time latching signal to a first receiving time marking signal; After receiving the delay request message, the processor sets a time stamp t4 pulse signal in a time stamp t4 pulse register to be 1; The time stamp processing module is used for responding to the rising edge of the time stamp t4 pulse signal and triggering the first receiving time stamp signal to be latched into a time stamp t4 register; The processor reads a time stamp t4 register, takes the read first receiving time stamp signal as a time stamp t4, marks the time stamp t4 on the delayed response message, and outputs a third Ethernet frame carrying the delayed response message to the slave clock node through the PTP sending module.
  4. 4. A time synchronization device is characterized in that the device is applied to a slave clock node in a precision time protocol PTP domain, the PTP domain also comprises a master clock node, the device comprises a processor and an FPGA, the FPGA comprises a time counter, a PCS receiving module, a PTP transmitting module and a time stamp processing module, A time counter for generating a time stamp in real time; The PCS receiving module is used for responding to the fifth Ethernet frame sent by the master clock node and outputting a second received data packet start identification SOP signal; the PTP receiving module is used for outputting a second receiving signal when analyzing the synchronous message in the fifth Ethernet frame; the time stamp processing module comprises a time stamp t12 latch register and a time stamp t12 register, and is used for assigning a third current time stamp acquired from the time counter to a second receiving time latch signal in response to a second receiving SOP signal, assigning the second receiving time latch signal to a second receiving time marking signal in response to the second receiving signal, and using the second receiving time marking signal as a time stamp t2 of the round and assigning a time stamp t1 of the round to the time stamp t12 register together, wherein the time stamp t1 is acquired based on the synchronous message or a received following message; A processor for generating a sixth ethernet frame carrying a delay request message; The PTP transmitting module is configured to output a second transmission data packet start identifier SOP signal in response to the sixth ethernet frame, output a second transmission signal when the delay request packet is parsed, and output the sixth ethernet frame to the master clock node; The time stamp processing module is used for responding to a second sending SOP signal, assigning a fourth current time stamp acquired from the time counter to a second sending time latching signal, and assigning the second sending time latching signal to a second sending time marking signal in response to the second sending signal; the PTP receiving module is used for analyzing a time stamp t4 carried by the delayed response message in the seventh Ethernet frame sent by the master clock node; the time stamp processing module is used for taking the second sending time stamp signal as a time stamp t3 of the round and assigning the time stamp t4 of the round to a time stamp t34 register together; The processor is used for reading the time stamp t1, the time stamp t2, the time stamp t3 and the time stamp t4 from the time stamp t12 register and the time stamp t34 register, and calculating to obtain time offset; A time counter that performs time synchronization based on the time offset; wherein the processor configuration supports a two-step mode, The PCS receiving module outputs a second received data packet start identification SOP signal when analyzing the SOP identification in the fifth Ethernet frame; The time stamp processing module responds to the rising edge of the second receiving SOP signal and assigns a third current time stamp acquired from the time counter to a second receiving time latch signal; The PTP receiving module continues to execute the analysis of the synchronous message in the fifth Ethernet frame, and responds to the MsgType field value in the synchronous message as 0 to output a second receiving signal; the timestamp processing module responds to the rising edge of the second receiving signal and assigns the second receiving time latching signal to a second receiving time marking signal; The PTP receiving module analyzes that a following message MsgType field value in an eighth Ethernet frame sent by the master clock node is 8, acquires a time stamp t1 in the following message, and outputs a receiving data packet end identifier EOP signal when the data packet end identifier EOP is analyzed; The time stamp processing module responds to the fact that a time stamp t12 latch enabling signal is 1, a MsgType field value is 8, a received EOP signal is 1, the second received time stamp signal is used as a time stamp t2 of the round, the time stamp t1 of the round is assigned to a time stamp t12 latch register together, the time stamp t12 latch enabling signal is set to zero, and the time stamp t12 latch enabling signal is used for indicating latch enabling of the time stamp t12 latch register; After the processor receives the synchronization message, the time stamp t12 latch enable signal is set to 1, and the time stamp t1 and the time stamp t2 in the time stamp t12 latch register are refreshed to the time stamp t12 register together.
  5. 5. The time synchronization device of claim 4, wherein the processor configuration supports a single step mode, The PCS receiving module outputs a second received data packet start identification SOP signal when analyzing the SOP identification in the fifth Ethernet frame; The time stamp processing module responds to the rising edge of the second receiving SOP signal and assigns a third current time stamp acquired from the time counter to a second receiving time latch signal; The PTP receiving module continues to execute the analysis of the synchronous message in the fifth Ethernet frame, and responds to the MsgType field value in the synchronous message as 0 to output a second receiving signal; the timestamp processing module responds to the rising edge of the second receiving signal and assigns the second receiving time latching signal to a second receiving time marking signal; the PTP receiving module continues to execute the analysis of the synchronous message, acquires a time stamp t1 in the synchronous message, and outputs a received data packet end identifier EOP signal when the analysis reaches the data packet end identifier EOP; The time stamp processing module responds to the fact that a time stamp t12 latch enabling signal is 1, a MsgType field value is 0, a received EOP signal is 1, the second received time stamp signal is used as a time stamp t2 of the round, the time stamp t1 of the round is assigned to a time stamp t12 latch register together, the time stamp t12 latch enabling signal is set to zero, and the time stamp t12 latch enabling signal is used for indicating latch enabling of the time stamp t12 latch register; After the processor receives the synchronization message, the time stamp t12 latch enable signal is set to 1, and the time stamp t1 and the time stamp t2 in the time stamp t12 latch register are refreshed to the time stamp t12 register together.
  6. 6. The apparatus of claim 5, wherein the time stamp processing module comprises a time stamp t34 latch register and a time stamp t34 register, The PTP sending module is configured to output an SOP signal of a second transmission data packet start identifier when the SOP identifier in the sixth ethernet frame is resolved; the timestamp processing module is used for responding to the rising edge of the second sending SOP signal and assigning a fourth current timestamp acquired from the time counter to a second sending time latching signal; The PTP sending module continues to execute the analysis of the delay request message in the sixth Ethernet frame, responds to the MsgType field value in the synchronous message as 0x01, outputs a second sending signal, and outputs the sixth Ethernet frame to the master clock node; the timestamp processing module responds to the rising edge of the second sending signal and assigns the second sending time latching signal to a second sending time marking signal; The PTP receiving module analyzes that a MsgType field value of a delay response message in a seventh Ethernet frame sent by the master clock node is 9, acquires a time stamp t4 in a following message, and outputs a received data packet end identifier EOP signal when the data packet end identifier EOP is analyzed; The time stamp processing module responds to the fact that a time stamp t34 latch enabling signal is 1, a MsgType field value is 9, an EOP signal is received to be 1, the second sending time stamp signal is used as a time stamp t3 of the round, the time stamp t4 of the round is assigned to a time stamp t34 latch register together, the time stamp t34 latch enabling signal is set to be zero, and the time stamp t34 latch enabling signal is used for indicating latch enabling of the time stamp t34 latch register; After the processor receives the delay response message, the time stamp t34 latch enable signal is set to 1, and the time stamp t3 and the time stamp t4 in the time stamp t34 latch register are refreshed to the time stamp t34 register together.
  7. 7. The apparatus of claim 6, wherein the time counter comprises a second counter, a nanosecond counter, a second offset register, and a nanosecond offset register, wherein, The nanosecond counter outputs a current nanosecond value; the second counter outputs a current second value; The processor writes a second offset value in the time offset into a second offset register, and writes a nanosecond offset value in the time offset into a nanosecond offset register, wherein the highest bit of the nanosecond offset register is a sign bit; if the sign bit represents a positive offset, a temporary nanosecond adjustment value is calculated, the temporary nanosecond adjustment value = current nanosecond value + nanosecond offset value +8, wherein, If the temporary nanosecond adjustment value exceeds 1 second, the adjusted nanosecond value=the temporary nanosecond adjustment value-1, and the adjusted second value=the current second value+the second offset value+1; if the temporary nanosecond adjustment value does not exceed 1 second, the adjusted nanosecond value is the temporary nanosecond adjustment value, and the adjusted second value=the current second value+the second offset value; If the sign bit represents a negative offset, a temporary nanosecond adjustment value is calculated, the temporary nanosecond adjustment value=the current nanosecond value+ (1-nanosecond offset value) +8, wherein, If the temporary nanosecond adjustment value exceeds 1 second, the adjusted nanosecond value=the temporary nanosecond adjustment value-1, and the adjusted second value=the current second value-second offset value; if the temporary nanosecond adjustment value does not exceed 1 second, the adjusted nanosecond value is the temporary nanosecond adjustment value, and the adjusted second value=the current second value-second offset value-1; the nanosecond counter performs nanosecond synchronization according to the adjusted nanosecond value, and the second counter performs second synchronization according to the adjusted second value.
  8. 8. A communication device comprising a time synchronizing device according to claims 1-3 and a time synchronizing device according to claims 4-7.

Description

Time synchronization device and communication equipment Technical Field The present application relates to the field of time synchronization technologies, and in particular, to a time synchronization device and a communication device. Background With the development of network technology, in a packet switched network or a data processing system, the requirement on time synchronization precision of system heavy equipment is higher and higher. At present, high-precision time synchronization is realized mainly based on an accurate time protocol (Precision Time Protocol, abbreviated as PTP) of a network measurement and control system. In the related technical scheme, the time synchronization is realized through PTP of software or hardware, and the problems that the time stamp precision is low due to the fact that the software scheme is adopted to receive the scheduling of an operating system, the influence of interrupt delay and the like generally, and the hardware scheme (such as a special PHY chip) is adopted, so that the problems of poor flexibility, high cost and the like exist, and the time synchronization precision of equipment under a complex network environment (such as high load, asymmetric links and the like) is low, and the requirement of microsecond or even nanosecond synchronization precision is difficult to meet. Disclosure of Invention The application aims to provide a time synchronization device which can realize high-precision time synchronization. In a first aspect, the present application provides a time synchronization device applied to a master clock node in a PTP domain of a precision time protocol, the PTP domain further including a slave clock node, the device including a processor and an FPGA, the FPGA including: A time counter for generating a time stamp in real time; the PTP sending module is used for responding to the received first Ethernet frame output by the processor, outputting a first sending data packet start identification (SOP) signal, and responding to the analyzed synchronous message in the first Ethernet frame, outputting a first sending signal; the time stamp processing module is used for assigning a first current time stamp acquired from the time counter to a first sending time latching signal in response to the first sending SOP signal, and assigning the first sending time latching signal to a time stamp t1 register in response to the first sending signal; The processor is used for reading a first sending time latching signal from the time stamp t1 register as a time stamp t1, marking the time stamp t1 for the synchronous message/the following message, and outputting the first Ethernet frame to a slave clock node through the FPGA; The FPGA further comprises: The PCS receiving module is used for responding to the second Ethernet frame output from the clock node and outputting a first received data packet start identification SOP signal; the PTP receiving module is used for responding to and analyzing a delay request message in the second Ethernet frame to output a first receiving signal; The time stamp processing module is used for assigning a second current time stamp acquired from the time counter to a first receiving time latch signal in response to the first receiving SOP signal and assigning the first receiving time latch signal to a time stamp t4 register in response to the first receiving signal; And the processor is used for reading the first receiving time latching signal from the time stamp t4 register as a time stamp t4, stamping the time stamp t4 on the delayed response message, and outputting a third Ethernet frame carrying the delayed response message to the slave clock node through the FPGA. Optionally, the time stamp processing module includes a time stamp t1 pulse register, the processor is configured to support a single step mode, The PTP sending module outputs a first sending SOP signal when analyzing the SOP identification of the first Ethernet frame; The time stamp processing module responds to the rising edge of the first sending SOP signal, obtains a first current time stamp from the time counter, and assigns the first current time stamp to a first sending time latching signal; the PTP sending module continues to execute the analysis of the synchronous message in the first Ethernet frame, and responds to the MsgType field value in the synchronous message as 0 to output a first sending signal; The time stamp processing module responds to the rising edge of the first sending signal, assigns the first sending time latching signal to a first sending time marking signal and sends the first sending time latching signal to the PTP sending module; The PTP sending module obtains the byte position of OriginTimestamp fields in the synchronous message by using a byte counting mode, adds a time stamp t1 indicated by the first sending time stamp signal to the byte position, and outputs a first Ethernet frame carrying the synchronous message to the slave clock n