CN-121364890-B - Fused instruction processor

CN121364890BCN 121364890 BCN121364890 BCN 121364890BCN-121364890-B

Abstract

The invention provides a fusion instruction processor, which belongs to the technical field of processors and comprises a decoding module, a plurality of conflict detection modules, a first operation module and an instruction execution module, wherein the decoding module decodes fusion instructions to be sent to obtain expected occupation time, the conflict detection modules respectively obtain conflict judgment results of whether a target hardware unit has resource conflict according to received expected occupation time and occupied time sequences stored locally and send control signals, and the first operation module determines whether to send the decoded fusion instructions to be sent according to the control signals sent by the conflict detection modules. The fused instruction processor provided by the invention effectively avoids the problem of resource conflict during processor operation from the fine granularity level of each micro-operation of the fused instruction and each hardware unit of the execution module, fully improves the operation efficiency, reduces the operation power consumption, exerts the hardware performance and greatly improves the instruction number executed per clock.

Inventors

HAO PENG
ZHOU XINBING
ZHANG SHENGBING

Assignees

西北工业大学

Dates

Publication Date: 20260505
Application Date: 20251222

Claims (8)

1. A fused instruction processor, comprising: The system comprises a decoding module, a plurality of conflict detection modules, a first operation module and an instruction execution module, wherein the instruction execution module comprises a plurality of hardware units for executing micro-operations of fusion instructions; the decoding module is used for decoding the fusion instruction to be sent to obtain each expected occupation moment and sending each expected occupation moment to each conflict detection module, wherein each expected occupation moment is the occupied moment of each hardware unit when the fusion instruction to be sent is executed; The conflict detection module is used for obtaining a conflict judgment result of whether the target hardware unit has resource conflict or not according to the received expected occupation time and a local occupied time sequence, and sending a control signal based on the conflict judgment result, wherein the received expected occupation time is the expected time when the target hardware unit is occupied when the fusion instruction to be sent is executed; the first operation module is used for determining whether to send the decoded fusion instruction to be sent or not according to the received control signals sent by the conflict detection modules; The instruction execution module is used for executing the decoded fusion instruction to be sent; the conflict detection module is further configured to, in a case where the received time sequence update signal is a first update signal, perform a first update operation based on the received expected occupied time and the occupied time sequence stored locally; executing a second update operation based on the locally stored occupied time sequence if the received time sequence update signal is a second update signal; the first updating signal is sent when the control signals sent by the conflict detection modules received by the first operation module are all permission sending signals, and the second updating signal is sent when the control signals sent by the conflict detection modules received by the first operation module comprise prohibition sending signals; The first updating operation is executed, which comprises the steps of carrying out OR operation on the occupied time sequence stored locally by utilizing the received expected occupied time to obtain an intermediate sequence, right shifting the intermediate sequence by one bit, and updating the occupied time sequence stored locally; The performing a second updating operation includes right shifting the locally stored occupied time series by one bit to update the locally stored occupied time series.
2. The fused instruction processor of claim 1, wherein the control signal is an enable signal or a disable signal, the collision detection module further comprising a second operation module; The second operation module is configured to obtain the conflict judgment result according to the received expected occupation time and the and operation result of the locally stored occupied time sequence; The conflict detection module is further configured to send a transmission prohibition signal when the conflict determination result indicates that the target hardware unit has a resource conflict, and send a transmission permission signal when the conflict determination result indicates that the target hardware unit does not have a resource conflict.
3. The fused instruction processor according to claim 2, wherein the determining whether to send the decoded fused instruction to be sent according to the received control signal sent by each collision detection module includes: under the condition that the received control signals sent by the conflict detection modules are all permission sending signals, determining to send the decoded fusion instruction to be sent; And under the condition that the received control signals sent by the conflict detection modules comprise forbidden sending signals, determining not to send the decoded fusion instruction to be sent.
4. The fused instruction processor of claim 2 wherein the conflict detection module includes a resource occupancy register for storing the occupied time sequence of the one hardware unit.
5. The fused instruction processor of claim 4 wherein a bit position of the resource occupancy register is used to represent occupancy time and a value of the bit position is used to represent occupancy status; the value of each bit position of the resource occupation register forms the occupied time sequence stored locally; Under the condition that the value of the bit position is 1, the occupied state of the target hardware unit in the occupied time is occupied; and under the condition that the value of the bit position is 0, the occupied state of the target hardware unit in the occupied time is idle.
6. The fused instruction processor of claim 5, wherein the first operation module is further configured to send a time sequence update signal according to the received control signal sent by each collision detection module, where the time sequence update signal is configured to instruct each collision detection module to update the occupied time sequence stored locally.
7. The fused instruction processor of claim 1, wherein the types of hardware units include arithmetic units and write-back units; the type of the arithmetic unit includes at least one of a multiplier, an adder, a logic operator, and a post-processing unit.
8. The fused instruction processor of claim 1, wherein the collision detection module and the first operation module are integrated on the decode module.

Description

Fused instruction processor Technical Field The invention relates to the technical field of processors, in particular to a fused instruction processor. Background Resource conflicts, also known as structural conflicts, structural hazards, refer to situations where two instructions are generated by the processor while using the same hardware. The method for solving the resource conflict mainly comprises (1) a mode of increasing hardware quantity, (2) a long pipeline blocking mode, wherein after each instruction sending, the instruction using the same hardware is not allowed to be sent before the instruction sending is completed in execution and a return execution result is written, and (3) a complete pipeline mode, namely an arithmetic logic unit (ARITHMETIC LOGIC UNIT) design of equal-length pipeline is adopted. However, the method of increasing the number of hardware causes high hardware cost, the long pipeline blocking method limits the performance of the processor, so that the processor cannot fully exert the hardware performance, and the fully pipelined method cannot exert the performance of the fused instruction although the resource conflict does not occur. Accordingly, there is a need to provide a fused instruction processor that can fully exhibit hardware performance without increasing hardware cost. Disclosure of Invention The invention provides a fused instruction processor which is used for solving the defects of the prior art in solving resource conflict in the aspects of increasing the number of hardware, blocking a long pipeline and fully pipelining, and realizing the fused instruction processor which does not need to increase the hardware cost and can fully exert the hardware performance. The invention provides a fusion instruction processor, comprising: The system comprises a decoding module, a plurality of conflict detection modules, a first operation module and an instruction execution module, wherein the instruction execution module comprises a plurality of hardware units for executing micro-operations of fusion instructions; the decoding module is used for decoding the fusion instruction to be sent to obtain each expected occupation moment and sending each expected occupation moment to each conflict detection module, wherein each expected occupation moment is the occupied moment of each hardware unit when the fusion instruction to be sent is executed; The conflict detection module is used for obtaining a conflict judgment result of whether the target hardware unit has resource conflict or not according to the received expected occupation time and a local occupied time sequence, and sending a control signal based on the conflict judgment result, wherein the received expected occupation time is the expected time when the target hardware unit is occupied when the fusion instruction to be sent is executed; the first operation module is used for determining whether to send the decoded fusion instruction to be sent or not according to the received control signals sent by the conflict detection modules; The instruction execution module is used for executing the decoded fusion instruction to be sent. The invention provides a fusion instruction processor, wherein the control signal is a transmission permission signal or a transmission prohibition signal; The second operation module is configured to obtain the conflict judgment result according to the received expected occupation time and the and operation result of the locally stored occupied time sequence; The conflict detection module is further configured to send a transmission prohibition signal when the conflict determination result indicates that the target hardware unit has a resource conflict, and send a transmission permission signal when the conflict determination result indicates that the target hardware unit does not have a resource conflict. According to the fusion instruction processor provided by the invention, the determination of whether to send the decoded fusion instruction to be sent according to the received control signals sent by the conflict detection modules comprises the following steps: under the condition that the received control signals sent by the conflict detection modules are all permission sending signals, determining to send the decoded fusion instruction to be sent; And under the condition that the received control signals sent by the conflict detection modules comprise forbidden sending signals, determining not to send the decoded fusion instruction to be sent. According to the fusion instruction processor provided by the invention, the conflict detection module comprises a resource occupation register, wherein the resource occupation register is used for storing the occupied time sequence of the hardware unit. According to the fusion instruction processor provided by the invention, the bit positions of the resource occupation register are used for representing the occupation time, and the values of the bit po