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CN-121364971-B - PCIe data link recovery method and PCIe system

CN121364971BCN 121364971 BCN121364971 BCN 121364971BCN-121364971-B

Abstract

The application provides a PCIe data link recovery method and a PCIe system, and relates to the technical field of PCIe communication. When the current board card is determined to be an EP end, MODprel signals are acquired, whether MODprel signals are low level is determined, a MODprel signal is used for indicating whether an optical module is in place, if MODprel signals are low level, a first RXLOS signal is acquired, whether the first RXLOS signal is low level is judged, if yes, an RSSI signal is acquired, a PCIe data link is reset according to the value of the RSSI signal, and the RSSI signal is used for representing the size of optical power. The application has the effect that the PCIe system can automatically reestablish the chain after the optical module or the optical fiber cable is plugged and unplugged.

Inventors

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Assignees

  • 成都星拓微电子科技股份有限公司

Dates

Publication Date
20260508
Application Date
20251030

Claims (10)

  1. 1. The PCIe data link recovery method is characterized by being applied to an MCU of an EP end in a PCIe system, wherein the EP end further comprises a retimer chip and an optical module, the MCU is respectively connected with the retimer chip and the optical module, and the method comprises the following steps: when the current board card is determined to be an EP end, a MODprel signal is obtained, and whether the MODprel signal is in a low level is determined, wherein the MODprel signal is used for indicating whether the optical module is in place or not; If MODprel signal is low level, acquiring a first RXLOS signal and judging whether the first RXLOS signal is low level, wherein the first RXLOS signal is used for indicating whether the optical signal is in place or not; If yes, acquiring an RSSI signal, and resetting a PCIe data link according to the value of the RSSI signal to recover the data link, wherein the RSSI signal is used for representing the size of optical power.
  2. 2. The PCIe data link recovery method of claim 1 wherein resetting the PCIe data link based on the value of the RSSI signal to recover the data link comprises: Resetting the PCIe data link when the value of the RSSI signal is greater than a threshold value; acquiring a second RXLOS signal and determining whether the second RXLOS signal is low level; if not, determining that the data link is restored; if so, determining whether to continue resetting the PCIe data link according to the number of times of resetting the PCIe data link.
  3. 3. The PCIe data link recovery method of claim 2 wherein the step of determining whether to continue resetting the PCIe data link based on the number of resets to the PCIe data link comprises: judging whether the number of resetting the PCIe data link is larger than a set value or not; if yes, generating a fault signal, and stopping resetting the PCIe data link; if not, resetting the PCIe data link again and controlling the counter to be incremented.
  4. 4. The PCIe data link recovery method of claim 2, wherein the EP end further includes a power supply unit, the power supply unit is configured to supply power to the retimer chips, and the power supply unit is connected to the MCU, and the step of resetting the PCIe data link includes: and controlling the power supply unit to execute the operation of powering down and powering up, or controlling the retimer chip to reset.
  5. 5. The PCIe data link recovery method of claim 1, wherein after the step of acquiring the RSSI signal, the method further comprises: Determining whether the RSSI signal has a return value; if yes, executing a step of resetting the PCIe data link according to the value of the RSSI signal; if not, the step of acquiring MODprel the signal and determining MODprel whether the signal is low is performed back.
  6. 6. The PCIe data link recovery method of claim 1, wherein prior to the step of determining that the current board card is the EP side, the method further comprises: when the terminal equipment selection pin of the MCU is a high-level signal, determining that the current board card is an EP terminal; and when the terminal equipment selection pin of the MCU is a low-level signal, determining that the current board card is an RC terminal.
  7. 7. The PCIe data link recovery method of claim 6, wherein after the step of determining that the current board card is the RC side, the method further comprises: Providing a normal power-on condition of the RC terminal and continuously acquiring signals of the optical module.
  8. 8. The PCIe data link recovery method of claim 1, wherein after the step of determining MODprel whether the signal is low, the method further comprises: When MODprel signal is high level, the MODprel signal is continuously acquired, and in the case where the acquisition MODprel signal jumps from high level to low level, the step of acquiring RSSI signal is performed.
  9. 9. The PCIe data link recovery method of claim 1, wherein after the step of determining whether the first RXLOS signal is low, the method further comprises: And if the first RXLOS signal is in a high level, determining that the data link works normally.
  10. 10. The PCIe system is characterized by comprising an RC end and an EP end, wherein the RC end and the EP end both comprise retimer chips and optical modules, the RC end and the EP end are connected through the optical modules, and the EP end further comprises an MCU (micro controller Unit) for executing the PCIe data link recovery method according to any one of claims 1 to 9.

Description

PCIe data link recovery method and PCIe system Technical Field The application relates to the technical field of PCIe communication, in particular to a PCIe data link recovery method and a PCIe system. Background PCIe (EPRIPHERAL COMPONENT INTERCONNECT EXPRESS, high speed serial computer expansion bus standard) interface is a standard interface to connect components to a computer. The uplink PCIe interface is used for communicating with a CPU (Central Processing Unit ) of the main board, the downlink interface is used for communicating with PCIe peripheral equipment, and dynamic configuration can be carried out through PCIe pseudo ports. Applications of PCIe typically involve the following: 1. In a high performance computing platform, the motherboard may integrate multiple CPUs, GPUs (Graphic Processing Unit, graphics processors), or other accelerators, and be connected via a PCIe bus. 2. In the high-performance storage solution, NVMe SSDs (Non-Volatile Memory Express Solid STATE DRIVE, nonvolatile memory expressing solid state disk) occupy a critical position, and multiple NVMe SSDs need to be connected to a motherboard through a PCIe bus. 3. Among a variety of AICs (Add-In Cards) including AI (ARTIFICIAL INTELLIGENCE ) accelerators, NIC (Network Interface Controller, network interface card) and memory expansion Cards, are also basically interconnected with server devices through PCIe interfaces. In the PCIe application scenario, the PCIe signal line path needs to be longer due to the problems of large-scale integration or size structure. Currently, a light transmission solution combining retimer (re-timer) technology and an optical module can be used. This combination is capable of supporting transmission distances up to tens of meters. When the optical fiber is used for high-speed data transmission, the retimer chip is beneficial to the conversion and recovery of the electric signal, and the problems of signal attenuation and distortion caused by the length and medium difference of the optical fiber are effectively solved. Therefore, the scheme not only ensures the data transmission rate and stability under long distance, but also provides flexible and reliable interconnection means for large-scale data centers. However, since the optical module itself has the characteristic of hot-pluggable, the optical fiber cable also has pluggable property, so that if a certain condition occurs (such as replacing the optical module or the optical fiber) after stable chain establishment transmission, the optical fiber is hot-plugged or plugged into the optical module, the data link will be interrupted, and after the optical path is restored, the PCIe system cannot autonomously complete the restoration of the chain, and after the RC (Root Complex) end or the EP (end point) is required to be manually intervened to restore, the whole PCIe system will restore the chain establishment, so that the flexibility will be poor, and inconvenience is caused to use. In summary, in the prior art, after the optical module performs hot plug or plugs the optical fiber, the PCIe system cannot autonomously complete the re-establishment of the chain. Disclosure of Invention The application aims to provide a PCIe data link recovery method and a PCIe system, which are used for solving the problem that the PCIe system cannot autonomously finish the re-establishment of a link after an optical module is subjected to hot plug or optical fiber plug in the prior art. In order to achieve the above object, the technical scheme adopted by the embodiment of the application is as follows: In one aspect, an embodiment of the present application provides a PCIe data link recovery method, where the method is applied to an MCU at an EP end in a PCIe system, where the EP end further includes a retimer chip and an optical module, and the MCU is connected to the retimer chip and the optical module respectively, and the method includes: when the current board card is determined to be an EP end, a MODprel signal is obtained, and whether the MODprel signal is in a low level is determined, wherein the MODprel signal is used for indicating whether the optical module is in place or not; If MODprel signal is low level, acquiring a first RXLOS signal and judging whether the first RXLOS signal is low level, wherein the first RXLOS signal is used for indicating whether the optical signal is in place or not; If yes, acquiring an RSSI signal, and resetting a PCIe data link according to the value of the RSSI signal to recover the data link, wherein the RSSI signal is used for representing the size of optical power. Optionally, resetting the PCIe data link according to the value of the RSSI signal, so that the step of recovering the data link includes: Resetting the PCIe data link when the value of the RSSI signal is greater than a threshold value; acquiring a second RXLOS signal and determining whether the second RXLOS signal is low level; if not, determining that the da