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CN-121419232-B - Semiconductor structure and manufacturing method thereof

CN121419232BCN 121419232 BCN121419232 BCN 121419232BCN-121419232-B

Abstract

The embodiment of the disclosure provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises a substrate and a plurality of memory cell transistors positioned on the substrate, each memory cell transistor comprises a nano-sheet group, a grid layer and a plurality of data storage elements, the nano-sheet group comprises a plurality of nano-sheets which are arranged at intervals and extend along a first direction, the nano-sheets comprise channel regions, the grid layer covers the plurality of channel regions of the nano-sheet group, the first direction is parallel to the surface of the substrate, the plurality of data storage elements are positioned on one side of the nano-sheet group along the first direction, and each data storage element is electrically connected with the plurality of nano-sheets of one memory cell transistor.

Inventors

  • LIU ZHIZHENG
  • LI ZONGHAN

Assignees

  • 长鑫芯瑞存储技术(北京)有限公司

Dates

Publication Date
20260508
Application Date
20251225

Claims (15)

  1. 1. A method of fabricating a semiconductor structure, comprising: forming an initial stacked structure on the substrate, wherein the initial stacked structure comprises first dielectric layers and stacked layers which are alternately stacked along a second direction, the stacked layers comprise a plurality of first semiconductor layers stacked along the second direction and second dielectric layers which are at least positioned between two adjacent first semiconductor layers, the initial stacked structure is patterned to form a plurality of stacked structures which extend along the first direction and are arranged along a third direction, the first semiconductor layers in the stacked structure are defined as initial nano-sheets, a part of the initial nano-sheets and a part of the second dielectric layers are removed along the first direction, so that second trenches which extend along the first direction are formed between the adjacent first dielectric layers, the rest of the initial nano-sheets form nano-sheets, the plurality of nano-sheets are spaced and extend along the first direction, the plurality of the nano-sheets positioned between the adjacent first dielectric layers form a plurality of nano-sheets, the nano-sheets are arranged along the first direction, the plurality of nano-sheets form a plurality of nano-sheets, and the nano-sheets are arranged along the first direction, the first nano-sheets form a plurality of channel region, and the nano-sheets are arranged on the surface of the substrate in a mode, and the nano-sheet is perpendicular to the first channel region; a plurality of data storage elements are formed, the data storage elements being located on one side of the set of nanoplates along the first direction and at least partially within the second trench, each of the data storage elements being electrically connected to a plurality of the nanoplates of one of the memory cell transistors.
  2. 2. The method of manufacturing according to claim 1, wherein the stacked structure has a first trench therebetween, the second trench being located at one side of the set of nano-sheets in the first direction and exposing sidewalls of a plurality of the nano-sheets in the set of nano-sheets; the method further includes filling an isolation layer in the first trench prior to forming the second trench.
  3. 3. The method of claim 1, further comprising performing an epitaxial process from the second trench to form an epitaxial layer covering at least sidewalls of the plurality of nanoplatelets in the set of nanoplatelets exposed by the second trench prior to forming the data storage element, the data storage element being in contact with the epitaxial layer.
  4. 4. The method of manufacturing according to claim 1 or 3, wherein a plurality of the nanosheet sets are arranged in a plurality of nanosheet rows and a plurality of nanosheet columns, the nanosheet rows extending along the third direction, each of the nanosheet rows including a plurality of the nanosheet sets arranged at intervals along the third direction, the nanosheet columns extending along the second direction, each of the nanosheet columns including a plurality of the nanosheet sets arranged at intervals along the second direction, forming the gate layer, comprising: Forming a plurality of word lines, each of the word lines extending in the second direction, the plurality of word lines being arranged in the third direction, Each word line corresponds to one nano sheet column, each word line covers part of the surfaces of a plurality of nano sheets in the corresponding nano sheet column, the word line covers part of a plurality of nano sheets of each nano sheet group to form a grid layer of the memory cell transistor, the plurality of grid layers of each nano sheet column are sequentially connected along the second direction to form the word line, and the part of the nano sheet covered by the word line forms the channel region.
  5. 5. The method of manufacturing of claim 4, wherein the nanoplatelets further comprise first source/drain regions located along the first direction on a side of the channel region facing away from the data storage element, the method further comprising forming a plurality of bit lines, each of the bit lines extending along the third direction, the plurality of bit lines being arranged along the second direction, wherein each of the bit lines corresponds to one of the nanoplatelet rows, each of the bit lines electrically connecting a plurality of the first source/drain regions in its corresponding nanoplatelet row.
  6. 6. The method of manufacturing according to claim 1 or 3, wherein a plurality of the nanosheet sets are arranged in a plurality of nanosheet rows and a plurality of nanosheet columns, the nanosheet rows extending along the third direction, each of the nanosheet rows including a plurality of the nanosheet sets arranged at intervals along the third direction, the nanosheet columns extending along the second direction, each of the nanosheet columns including a plurality of the nanosheet sets arranged at intervals along the second direction, forming the gate layer, comprising: forming a plurality of word lines, each of the word lines extending in the third direction, the plurality of word lines being arranged in the second direction, Each word line corresponds to one nano sheet row, each word line covers part of the surfaces of a plurality of nano sheets in the corresponding nano sheet row, each word line covers part of a plurality of nano sheets in each nano sheet group to form a grid layer of the memory cell transistor, the plurality of grid layers of each nano sheet row are sequentially connected along the third direction to form the word line, and the part of the nano sheet covered by the word line forms the channel region.
  7. 7. The method of manufacturing of claim 6, wherein the nanoplatelets further comprise first source/drain regions located along the first direction on a side of the channel region facing away from the data storage element, the method further comprising forming a plurality of bit lines, each of the bit lines extending along the second direction, the plurality of bit lines being arranged along the third direction, wherein each of the bit lines corresponds to one of the nanoplatelet columns, each of the bit lines electrically connecting a plurality of the first source/drain regions in its corresponding nanoplatelet column.
  8. 8. The method of manufacturing of claim 1, wherein forming the initial stacked structure on the substrate comprises: Forming a stacked material layer on the substrate, the stacked material layer including second semiconductor layers and an initial stacked layer alternately stacked in the second direction, the initial stacked layer including a plurality of the first semiconductor layers stacked in the second direction, and a third semiconductor layer located at least between two adjacent first semiconductor layers; removing at least part of the second semiconductor layer to form a first gap; Filling the first medium layer in the first gap; removing at least part of the third semiconductor layer to form a second gap; and filling the second medium layer in the second gap.
  9. 9. The method of claim 8, wherein the second semiconductor layer and the third semiconductor layer each comprise silicon germanium, wherein the atomic percent of germanium atoms in the second semiconductor layer is between 0.2 and 0.5, wherein the atomic percent of germanium atoms in the third semiconductor layer is between 0.1 and 0.2, and/or, In the step of removing at least a part of the second semiconductor layer, an etching selectivity ratio of the second semiconductor layer to the third semiconductor layer is 100 or more, and/or, In the step of removing at least part of the third semiconductor layer, an etching selectivity ratio of the third semiconductor layer to the first semiconductor layer is greater than or equal to 100.
  10. 10. A semiconductor structure made by the method of any of claims 1-9, the semiconductor structure comprising: The memory cell comprises a substrate, a plurality of memory cell transistors positioned on the substrate, a grid layer, a first storage layer and a second storage layer, wherein each memory cell transistor comprises a nano sheet group, the nano sheet group comprises a plurality of nano sheets which are arranged at intervals and extend along a first direction, and the nano sheets comprise channel regions; A plurality of data storage elements located on one side of the set of nanoplates along the first direction, each of the data storage elements being electrically connected to a plurality of the nanoplates of one of the memory cell transistors.
  11. 11. The semiconductor structure of claim 10, wherein the memory cell transistor further comprises an epitaxial layer covering at least a sidewall of the plurality of the nanoplatelets of the set of nanoplatelets proximate to the data storage element, the data storage element being in contact with the epitaxial layer.
  12. 12. The semiconductor structure of claim 10, wherein each of the sets of nanoplatelets comprises 2 or 3 nanoplatelets, and/or wherein the plurality of nanoplatelets of each of the sets of nanoplatelets are spaced apart along a second direction, the second direction being perpendicular to the surface of the substrate.
  13. 13. The semiconductor structure of any one of claims 10-12, wherein a plurality of the memory cell transistors are arranged in a plurality of transistor rows and a plurality of transistor columns, the transistor rows extending along a third direction, each of the transistor rows including a plurality of memory cell transistors arranged at intervals along the third direction, the third direction intersecting the first direction and being parallel to a surface of the substrate; The transistor columns extend along a second direction, each transistor column comprises a plurality of memory cell transistors which are arranged at intervals along the second direction, and the second direction is perpendicular to the surface of the substrate.
  14. 14. The semiconductor structure of claim 13, wherein the gate layers extend in the second direction, the plurality of gate layers of each transistor column being connected in sequence in the second direction to form a plurality of word lines, the plurality of word lines extending in the second direction and being arranged in the third direction; The nano-sheet further comprises a first source/drain region, wherein the first source/drain region is located on one side, away from the data storage element, of the channel region along the first direction, the semiconductor structure further comprises a plurality of bit lines, each bit line extends along the third direction, the bit lines are arranged along the second direction, each bit line corresponds to one transistor row, and each bit line is electrically connected with the first source/drain regions in the corresponding transistor row.
  15. 15. The semiconductor structure of claim 13, wherein the gate layers extend along the third direction, the plurality of gate layers of each transistor row being connected in sequence along the third direction to form a plurality of word lines, the plurality of word lines extending along the third direction and being arranged along the second direction; The nano-sheet further comprises a first source/drain region, wherein the first source/drain region is located on one side, away from the data storage element, of the channel region along the first direction, the semiconductor structure further comprises a plurality of bit lines, each bit line extends along the second direction, the bit lines are distributed along the third direction, each bit line corresponds to one transistor column, and each bit line is electrically connected with the first source/drain regions in the corresponding transistor column.

Description

Semiconductor structure and manufacturing method thereof Technical Field The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the same. Background The dynamic random access memory Dynamic.Random.Access.Memory, DRAM is a semiconductor device commonly used in electronic equipment such as a computer. The array region of a DRAM chip typically includes an array of 3D stacked memory cells. The DRAM access transistor needs to have low leakage characteristics and high on-current, and with the continuous development of semiconductor structures, the critical dimensions thereof are continuously reduced, and how to improve the gate control capability is a problem to be solved. Disclosure of Invention Embodiments of the present disclosure provide a semiconductor structure, comprising: The memory cell comprises a substrate, a plurality of memory cell transistors positioned on the substrate, a grid layer, a first storage layer and a second storage layer, wherein each memory cell transistor comprises a nano sheet group, the nano sheet group comprises a plurality of nano sheets which are arranged at intervals and extend along a first direction, and the nano sheets comprise channel regions; A plurality of data storage elements located on one side of the set of nanoplates along the first direction, each of the data storage elements being electrically connected to a plurality of the nanoplates of one of the memory cell transistors. In some embodiments, the memory cell transistor further comprises an epitaxial layer covering at least a sidewall of the plurality of the nanoplatelets of the set of nanoplatelets proximate to the data storage element, the data storage element being in contact with the epitaxial layer. In some embodiments, each of the nanoplatelet sets comprises 2 or 3 nanoplatelets, and/or the plurality of nanoplatelets of each of the nanoplatelet sets are arranged at intervals along a second direction, the second direction being perpendicular to the surface of the substrate. In some embodiments, the plurality of memory cell transistors are arranged in a plurality of transistor rows and a plurality of transistor columns, the transistor rows extending along a third direction, each of the transistor rows including a plurality of memory cell transistors arranged at intervals along the third direction; The transistor columns extend along a second direction, each transistor column comprises a plurality of memory cell transistors which are arranged at intervals along the second direction, and the second direction is perpendicular to the surface of the substrate. In some embodiments, the gate layers extend along the second direction, and the gate layers of each transistor column are sequentially connected along the second direction to form word lines, the number of the word lines is plural, and the word lines extend along the second direction and are arranged along the third direction; The nano-sheet further comprises a first source/drain region, wherein the first source/drain region is located on one side, away from the data storage element, of the channel region along the first direction, the semiconductor structure further comprises a plurality of bit lines, each bit line extends along the third direction, the bit lines are arranged along the second direction, each bit line corresponds to one transistor row, and each bit line is electrically connected with the first source/drain regions in the corresponding transistor row. In some embodiments, the gate layers extend along the third direction, the gate layers of each transistor row are sequentially connected along the third direction to form word lines, the number of the word lines is plural, and the word lines extend along the third direction and are arranged along the second direction; The nano-sheet further comprises a first source/drain region, wherein the first source/drain region is located on one side, away from the data storage element, of the channel region along the first direction, the semiconductor structure further comprises a plurality of bit lines, each bit line extends along the second direction, the bit lines are distributed along the third direction, each bit line corresponds to one transistor column, and each bit line is electrically connected with the first source/drain regions in the corresponding transistor column. The embodiment of the disclosure also provides a manufacturing method of the semiconductor structure, which comprises the following steps: Providing a substrate and forming a plurality of memory cell transistors on the substrate, wherein forming the memory cell transistors comprises forming a nano-sheet group comprising a plurality of nano-sheets which are arranged at intervals and extend along a first direction, wherein the nano-sheets comprise channel regions; A plurality of data storage elements are formed, the data storage elements bein