CN-121434152-B - System-on-chip, storage module and system interface parameter training method and device

CN121434152BCN 121434152 BCN121434152 BCN 121434152BCN-121434152-B

Abstract

The invention relates to the technical field of chip design, in particular to a system-on-chip, a storage module, a system interface parameter training method and device, wherein the system-on-chip can communicate with a memory and comprises at least one of a reference voltage adjusting module, a calibration resistance adjusting module and a delay control module, wherein the reference voltage adjusting module is used for performing reference voltage value training to obtain a target reference voltage value, the system-on-chip communicates with the memory based on the target reference voltage value, the calibration resistance adjusting module is used for performing calibration resistance value training to obtain a target calibration resistance value, the system-on-chip communicates with the memory based on the target calibration resistance value, and the delay control module is used for performing signal delay value training to obtain a target signal delay value, and the system-on-chip communicates with the memory based on the target signal delay value. The data interaction reliability of the system-on-chip is improved.

Inventors

CHEN ZEFU
Dong Wangfei
WANG GANG

Assignees

珠海奔图电子有限公司

Dates

Publication Date: 20260512
Application Date: 20251231

Claims (15)

1. A system-on-chip capable of communicating with a memory includes a reference voltage adjustment module, at least one of a calibration resistance adjustment module and a delay control module, wherein, The reference voltage adjusting module is used for performing reference voltage value training to obtain a target reference voltage value, and the system on chip and the memory are communicated based on the target reference voltage value; the calibration resistance adjustment module is used for performing calibration resistance training to obtain a target calibration resistance, and the system-on-chip and the memory communicate based on the target calibration resistance; the delay control module is used for executing signal delay value training to obtain a target signal delay value, and the system on chip and the memory are communicated based on the target signal delay value; The delay control module obtains a target signal delay value through the following system interface parameter training method: determining a first signal delay value boundary based on the initial signal delay value and a first signal delay value correction step size; Determining a second signal delay value boundary based on the first signal delay value boundary and a second signal delay value correction step length, wherein the second signal delay value correction step length is smaller than the first signal delay value correction step length; Determining a third signal delay value boundary based on the first signal delay value correction step size and the second signal delay value boundary, wherein the third signal delay value boundary is larger than the second signal delay value boundary; and determining a difference value average value between the second signal delay value boundary and the third signal delay value boundary as a target signal delay value, wherein the signal is a data strobe signal or a data signal when the delay control module comprises a data delay sub-module, the signal is an address signal when the delay control module comprises an address delay sub-module, and the signal is a command signal when the delay control module comprises a command delay sub-module.
2. The system on a chip of claim 1, wherein the latency control module comprises at least one of a data latency sub-module, an address latency sub-module, and a command latency sub-module; The data delay sub-module is configured to perform data strobe signal delay training to obtain a target data strobe signal delay value, and/or perform data signal delay training to obtain a target data signal delay value, where the system on chip and the memory communicate based on the target data strobe signal delay value and/or the target data signal delay value; The address delay sub-module is used for executing address signal delay training to obtain a target address signal delay value, and the system on chip and the memory are communicated based on the target address signal delay value; the command delay sub-module is used for executing command signal delay training to obtain a target command signal delay value, and the system-on-chip and the memory are communicated based on the target command signal delay value.
3. The system on a chip of claim 1, wherein the reference voltage adjustment module obtains the target reference voltage value by a system interface parameter training method comprising: Step a1, determining an initial reference voltage value and an initial voltage correction step length; Step b1, indicating the system-on-chip to interact test data with the memory based on a first reference voltage value, and determining a first time sequence window size associated with the first reference voltage value, wherein the first reference voltage value is a difference value between the initial reference voltage value and the initial voltage correction step; step c1, indicating the system-on-chip to interact test data with the memory based on a second reference voltage value, and determining a second time sequence window size associated with the second reference voltage value, wherein the second reference voltage value is the sum value of the initial reference voltage value and the initial voltage correction step; And d1, when the first time sequence window size and the second time sequence window size are equal, determining the initial reference voltage value as a target reference voltage value.
4. The system on a chip of claim 3, further comprising: When the first time sequence window size is determined to be unequal to the second time sequence window size, the following steps are repeatedly executed: updating the initial reference voltage value and the initial voltage correction step length; executing the step b1 and the step c1 based on the updated initial reference voltage value and the updated initial voltage correction step; until the first timing window size is equal to the second timing window size.
5. The system on a chip of claim 4, wherein the updating the initial reference voltage value and the initial voltage correction step size comprises: when the first time sequence window size is larger than the second time sequence window size, updating the initial reference voltage value to be the first reference voltage value, and reducing the initial voltage correction step size; And when the first time sequence window size is smaller than the second time sequence window size, updating the initial reference voltage value to be the second reference voltage value, and reducing the initial voltage correction step size.
6. The system on a chip of claim 1, wherein the calibration resistance adjustment module obtains the target calibration resistance value by a system interface parameter training method comprising: Step a2, determining an initial calibration resistance value and an initial resistance correction step length; Step b2, indicating the system-on-chip to exchange test data with the memory based on a first calibration resistance value, and determining a third time sequence window size associated with the first calibration resistance value, wherein the first calibration resistance value is a difference value between the initial calibration resistance value and the initial resistance correction step; Step c2, indicating the system-on-chip to exchange test data with the memory based on a second calibration resistance value, and determining a fourth timing window size associated with the second calibration resistance value, wherein the second calibration resistance value is the sum of the initial calibration resistance value and the initial resistance correction step length; and d2, when the third time sequence window size and the fourth time sequence window size are determined to be equal, determining the initial calibration resistance value as a target calibration resistance value.
7. The system on a chip of claim 6, further comprising: when the third timing window size is determined to be unequal to the fourth timing window size, repeating the steps of: updating the initial calibration resistance value and the initial resistance correction step length; Executing the step b2 and the step c2 based on the updated initial calibration resistance value and the updated initial resistance correction step; Until the third timing window size is equal to the fourth timing window size.
8. The system on a chip of claim 7, wherein the updating the initial calibration resistance value and the initial resistance correction step size comprises: When the third time sequence window size is larger than the fourth time sequence window size, updating the initial calibration resistance value to be the first calibration resistance value, and reducing the initial resistance correction step length; and when the third time sequence window size is smaller than the fourth time sequence window size, updating the initial calibration resistance value to be the second calibration resistance value, and reducing the initial resistance correction step size.
9. The system on a chip of claim 1, wherein the determining the first signal delay value boundary based on the initial signal delay value and the first signal delay value correction step size comprises: Determining the sum of the initial signal delay value and the first signal delay value correction step length to obtain a first test signal delay value; Indicating the system-on-chip and memory interaction test data based on the first test signal delay value; if the process of the system-on-chip and the memory interactive test data is not wrong, the following steps are repeatedly executed: Determining the first test signal delay value as the updated initial signal delay value; determining the sum of the updated initial signal delay value and the first signal delay value correction step length to obtain an updated first test signal delay value; indicating the system-on-chip and the memory to interact with test data based on the updated first test signal delay value; and determining the updated first test signal delay value as the first signal delay value boundary until the error occurs in the process of the interaction test data between the system on chip and the memory.
10. The system on a chip of claim 1, wherein the determining the second signal delay value boundary based on the first signal delay value boundary and a second signal delay value correction step size comprises: determining the difference value of the first signal delay value boundary and the second signal delay value correction step length to obtain a second test signal delay value; indicating the system-on-chip and memory interaction test data based on the second test signal delay value; if the process of the system-on-chip and the memory interactive test data is wrong, the following steps are repeatedly executed: Determining the second test signal delay value as an updated first signal delay value boundary; Determining a difference value between the updated first signal delay value boundary and the second signal delay value correction step length to obtain an updated second test signal delay value; indicating the system-on-chip to interact test data with the memory based on the updated second test signal delay value; and determining the updated second test signal delay value as the boundary of the second signal delay value until the process of the system-on-chip and the memory interactive test data is not in error.
11. The system on a chip of claim 1, wherein the determining a third signal delay value boundary based on the first signal delay value correction step size and the second signal delay value boundary comprises: Determining the boundary of the second signal delay value and the sum value between the correction step sizes of the first signal delay value to obtain a third test signal delay value; Indicating the system-on-chip and memory interaction test data based on the third test signal delay value; if the process of the system-on-chip and the memory interactive test data is not wrong, the following steps are repeatedly executed: determining the third test signal delay value as an updated second signal delay value boundary; determining the sum value between the updated second signal delay value boundary and the first signal delay value correction step length to obtain the updated third test signal delay value; indicating the system-on-chip and the memory to interact with test data based on the updated third test signal delay value; And determining the updated third test signal delay value as the third signal delay value boundary until the error occurs in the process of the system-on-chip and the memory interactive test data.
12. The system on a chip of claim 1, wherein the step of correcting the step size based on the first signal delay value and the second signal delay value boundary, after determining a third signal delay value boundary, further comprises: based on the third signal delay value boundary and the second signal delay value correction step length, a fourth signal delay value boundary is obtained; And determining the fourth signal delay value boundary as the adjusted third signal delay value boundary.
13. The system on a chip of claim 12, wherein the correcting step based on the third signal delay value boundary and the second signal delay value to obtain a fourth signal delay value boundary comprises: Determining a difference value between the third signal delay value boundary and the second signal delay value correction step length to obtain a fourth test signal delay value; Indicating the system-on-chip and memory interaction test data based on the fourth test signal delay value; if the process of the system-on-chip and the memory interactive test data is wrong, the following steps are repeatedly executed: determining the fourth test signal delay value as an updated third signal delay value boundary; determining the difference value of the updated third signal delay value boundary and the second signal delay value correction step length to obtain the updated fourth test signal delay value; indicating the system-on-chip and the memory to interact with test data based on the updated fourth test signal delay value; And determining a corresponding updated fourth test signal delay value as a fourth signal delay value boundary until the process of the system-on-chip and the memory interactive test data is not in error.
14. A memory module comprising the system on chip of claim 1, and a memory in communication with the system on chip.
15. An electronic device comprising a memory module as claimed in claim 14, wherein the reference voltage adjustment module in the system-on-chip of the memory module is configured to perform a reference voltage value training to obtain a target reference voltage value, wherein the system-on-chip communicates with the memory based on the target reference voltage value, and/or wherein, The calibration resistance adjustment module in the system-on-chip is configured to perform calibration resistance training to obtain a target calibration resistance, the system-on-chip is in communication with the memory based on the target calibration resistance, and/or, The delay control module in the system on chip is used for executing signal delay value training to obtain a target signal delay value, and the system on chip is communicated with the memory based on the target signal delay value; The delay control module obtains a target signal delay value through the following system interface parameter training method: determining a first signal delay value boundary based on the initial signal delay value and a first signal delay value correction step size; Determining a second signal delay value boundary based on the first signal delay value boundary and a second signal delay value correction step length, wherein the second signal delay value correction step length is smaller than the first signal delay value correction step length; Determining a third signal delay value boundary based on the first signal delay value correction step size and the second signal delay value boundary, wherein the third signal delay value boundary is larger than the second signal delay value boundary; and determining a difference value average value between the second signal delay value boundary and the third signal delay value boundary as a target signal delay value, wherein the signal is a data strobe signal or a data signal when the delay control module comprises a data delay sub-module, the signal is an address signal when the delay control module comprises an address delay sub-module, and the signal is a command signal when the delay control module comprises a command delay sub-module.

Description

System-on-chip, storage module and system interface parameter training method and device Technical Field The disclosure relates to the technical field of chip design, and in particular relates to a system on chip, a storage module and a system interface parameter training method and device. Background Data read-write and instruction processing are basic settings in electronic devices through a Memory module composed of a System on Chip (SoC) and a volatile Memory, wherein a double data rate synchronous dynamic random Access Memory (DDR SDRAM) interface is also widely used as a common data communication interface in the Memory module. In the related art, after the memory module is powered on, appropriate module operation parameters such as calibration resistance, reference voltage, data strobe (Data Queue Strobe, DQS) signal delay, address command delay and the like need to be initialized for the memory module, so that communication between the system on chip and the memory based on the DDR interface can be normally performed. However, the initialization scheme of the module operation parameters provided in the related art generally easily causes the problem of abnormal initialization of the memory module or abnormal operation after initialization, resulting in reduced operation reliability of the memory module. Disclosure of Invention The present disclosure has been made in view of the above-described problems. The present disclosure provides a system on chip, a storage module, and a system interface parameter training method and apparatus, which can improve the data interaction reliability of the system on chip. According to a first aspect of the present disclosure, a system on a chip is provided, the system on a chip being capable of communicating with a memory, comprising at least one of a reference voltage adjustment module, a calibration resistance adjustment module and a delay control module, wherein, The reference voltage adjusting module is used for performing reference voltage value training to obtain a target reference voltage value, and the system on chip and the memory are communicated based on the target reference voltage value; the calibration resistance adjustment module is used for performing calibration resistance training to obtain a target calibration resistance, and the system-on-chip and the memory communicate based on the target calibration resistance; The delay control module is used for executing signal delay value training to obtain a target signal delay value, and the system on chip is communicated with the memory based on the target signal delay value. In one embodiment, the delay control module comprises at least one of a data delay sub-module, an address delay sub-module and a command delay sub-module, wherein the data delay sub-module is used for executing data strobe signal delay training to obtain a target data strobe signal delay value and/or executing data signal delay training to obtain a target data signal delay value, the system on chip and the memory are communicated based on the target data strobe signal delay value and/or the target data signal delay value, the address delay sub-module is used for executing address signal delay training to obtain a target address signal delay value, the system on chip and the memory are communicated based on the target address signal delay value, and the command delay sub-module is used for executing command signal delay training to obtain a target command signal delay value, and the system on chip and the memory are communicated based on the target command signal delay value. According to a second aspect of the present disclosure, there is provided a memory module comprising the system on chip of the first aspect, and a memory in communication with the system on chip. According to a third aspect of the present disclosure, there is provided a system interface parameter training method, the method being applied to the memory module set according to the second aspect, the system on chip in the memory module set including a reference voltage adjustment module, the method comprising: Step a1, determining an initial reference voltage value and an initial voltage correction step length; Step b1, indicating the system-on-chip to interact test data with the memory based on a first reference voltage value, and determining a first time sequence window size associated with the first reference voltage value, wherein the first reference voltage value is a difference value between the initial reference voltage value and the initial voltage correction step; step c1, indicating the system-on-chip to interact test data with the memory based on a second reference voltage value, and determining a second time sequence window size associated with the second reference voltage value, wherein the second reference voltage value is the sum value of the initial reference voltage value and the initial voltage correction step; And d1, when the first time sequence