CN-121441856-B - UCIe standard protocol layer data transmission circuit, related method and chip

CN121441856BCN 121441856 BCN121441856 BCN 121441856BCN-121441856-B

Abstract

The application provides a UCIe standard protocol layer data transmission circuit, a related method and a chip, wherein the circuit comprises a slicing circuit, a framing device, a flow control unit Flit, a deframer and a packet grouping circuit, wherein the slicing circuit is configured to slice a data packet from a service port, the framing device is configured to send slice frames and slice description information related to the slice frames to the framing device, the framing device is configured to fill slice frames from the slicing devices and slice description information related to the slice frames to the flow control unit Flit, the deframer is configured to send Flit to the deframer, the deframer is configured to determine slice frames belonging to the same service port from the Flit, and send the slice frames and the slice description information related to the slice frames to the packet grouping circuit corresponding to the service port, and the packet grouping circuit is configured to splice data slices belonging to the same data packet in the slice frames and output the data packet based on the slice description information. The method solves the technical problem that the prior UCIe standard protocol layer data transmission needs to introduce a large multiplexer, so that the additional delay is introduced due to the insertion.

Inventors

GUO XIANGYU

Assignees

格创通信(浙江)有限公司

Dates

Publication Date: 20260512
Application Date: 20251231

Claims (7)

1. A UCIe standard protocol layer data transmission circuit, comprising: The device comprises a framing device, a deframer, N slicing circuits corresponding to service ports and N packet grouping circuits corresponding to the service ports; The slicing circuit is configured to slice the data packet from the service port based on the byte length M to obtain a data slice, send a slice frame to the framing device and slice description information associated with the slice frame, wherein M is a predetermined fixed value; The slice description information includes: Information describing the last slice of the data packet; the data slice frame is used for displaying the data slices in the data slice frame; The type of the slice frame is divided based on the validity and the homology of the data slice in the slice frame; An end identifier and a byte length identifier; When the classification mark indicates that the data slices in the slice frame are all valid and belong to the same data packet, the end mark is used for indicating whether the first data slice in the slice frame is the beginning of the data packet and whether the last data slice is the end of the data packet; When the classification mark indicates that the data slices in the slice frame are all valid and belong to different data packets, the end mark is used for indicating the end slice of the data packet of the previous data packet in the slice frame, and the byte length mark is used for indicating whether the byte length of the end slice of the data packet of the previous data packet in the slice frame reaches M; the framer is configured to fill a flow control unit Flit with slice frames from the slicing circuits and the slice description information associated with the slice frames, and send the Flit to the deframer; The deframer is configured to determine slice frames belonging to the same service port from the Flit, and send the slice frames and the slice description information associated with the slice frames to a packet circuit corresponding to the service port; And the packet grouping circuit is configured to splice the data slices belonging to the same data packet in the slice frame and output the data packet by taking the data slices as a scheduling unit based on the slice description information.
2. The circuit of claim 1, wherein the slicing circuit comprises: a slice storage unit, a first MUX group, a first FIFO group, and a second MUX group; The slice storage unit is configured to store data slices segmented based on spliced data, wherein the data slices comprise a first data slice and a second data slice, the first data slice comprises a data slice with a byte length of M at the end of a non-data packet or a data slice with a byte length of less than or equal to M at the end of the data packet, and the second data slice comprises a data slice with a byte length of less than M at the end of the non-data packet; The first MUX group is configured to write the first data slice to the first FIFO group in cycles; The second MUX group is configured to cyclically read the first data slice from the first FIFO group and send it to the framer.
3. The circuit of claim 2, wherein the slicing circuit further comprises an invalid slice filling unit; the invalid slice filling unit is configured to fill invalid data slices into the first FIFO group when the number of data slices in the first FIFO group does not reach a first number, the first number being the number of data slices read out by the second MUX group per round of rotation.
4. The circuit of claim 1, wherein the pack circuit comprises: a third MUX group, a second FIFO group, a fourth MUX group, a read cache group, an end cache, and a fifth MUX group; The third MUX group is configured to cyclically write valid data slices from the deframer into the second FIFO group, wherein the validity of the data slices is determined based on the slice description information; The fourth MUX group is configured to read the data slice from the second FIFO group and write the data slice into the read cache group in a rotating way under the condition that the writing condition is met, wherein the writing condition comprises that the read cache group contains idle read caches and the read cache group does not contain the tail slice of the data packet; The tail buffer is configured to store low-order data with byte length smaller than M in the residual data, wherein the residual data represents the data after the packet circuit outputs the low-order data in the tail buffer and the read buffer group; The fifth MUX group is configured to determine low-order data with preset output bit width from the tail buffer memory and the read buffer memory group and output the low-order data under the condition that a first output condition is met, wherein the first output condition comprises that the sum of the data lengths in the tail buffer memory and the read buffer memory group exceeds the preset output bit width; The fifth MUX group is configured to determine and output the end data of the data packet which does not exceed the preset output bit width from the end buffer memory and the read buffer memory group under the condition that a second output condition is met, wherein the second output condition comprises that the end buffer memory or the read buffer memory group contains the end slice of the data packet.
5. The circuit of claim 1, wherein the slice description information further comprises port indication information, the port indication information being used to indicate a traffic port to which the slice frame belongs.
6. A method for transmitting protocol layer data in UCIe standard, the method comprising: Dividing data packets from N service ports based on byte length M to obtain data slices, wherein M is a predetermined fixed value; Generating a slice frame and slice description information associated with each slice frame, wherein the slice frame comprises a preset number of data slices; The slice description information includes: Information describing the last slice of the data packet; the data slice frame is used for displaying the data slices in the data slice frame; The type of the slice frame is divided based on the validity and the homology of the data slice in the slice frame; An end identifier and a byte length identifier; When the classification mark indicates that the data slices in the slice frame are all valid and belong to the same data packet, the end mark is used for indicating whether the first data slice in the slice frame is the beginning of the data packet and whether the last data slice is the end of the data packet; When the classification mark indicates that the data slices in the slice frame are all valid and belong to different data packets, the end mark is used for indicating the end slice of the data packet of the previous data packet in the slice frame, and the byte length mark is used for indicating whether the byte length of the end slice of the data packet of the previous data packet in the slice frame reaches M; Filling slice frames corresponding to the service ports and the slice description information associated with the slice frames into a flow control unit Flit and sending the Flit through a preset interface; the method further comprises the steps of: receiving a flow control unit Flit through a preset interface; Determining a slice frame belonging to each service port from the Flit and slice description information associated with the slice frame, wherein the slice frame comprises a preset number of data slices; and for each service port, based on the slice description information, splicing the data slices belonging to the same data packet in the slice frame by taking the data slices as scheduling units to obtain the data packet.
7. A chip comprising a plurality of die through a die interconnect interface, wherein the die interconnect interface comprises the UCIe standard protocol layer data transfer circuit of any one of claims 1 to 5.

Description

UCIe standard protocol layer data transmission circuit, related method and chip Technical Field The present application relates to the field of integrated circuit design technologies, and in particular, to a UCIe standard protocol layer data transmission circuit, a related method and a chip. Background In recent years, it has become more difficult to increase the on-chip transistor density and thus the performance by process improvements, and advanced processes are costly. For the purpose of further improving the computing power and reducing the cost, the industry has begun to use the core (Chiplet) technology. That is, the functionality of a single large chip is divided into several small die, each of which can be manufactured independently and finally integrated together by packaging techniques. Each Die above may be referred to as a Die (Die). Currently, vendors typically use Chiplet technology to offload communication-related functions onto dedicated cores, but introducing Chiplet technology introduces additional delay, so it is necessary to reduce the delay as much as possible. Due to physical implementation limitations, the physical and adaptation layers of the universal chiplet interconnect bus (Universal Chiplet Interconnect Express, UCIe) standard are relatively delayed, and to effectively reduce the delay across Die, a low-delay protocol layer needs to be developed. In the related art, input data packets are spliced end to end, and the load part of the flow control unit (Flow Control Unit, flit) is filled in a flow manner, which results in a relatively complex circuit structure. In addition, a large communication overhead is required in order to identify the packet boundary. Disclosure of Invention The embodiment of the application provides a UCIe standard protocol layer data transmission circuit, a related method and a chip, which are used for solving the technical problem that the prior UCIe standard protocol layer data transmission needs to introduce a large multiplexer, so that the insertion is caused to introduce extra delay. According to a first aspect of the present application, there is provided a UCIe standard protocol layer data transmission circuit, including: The device comprises a framing device, a deframer, N slicing circuits corresponding to service ports and N packet grouping circuits corresponding to the service ports; The slicing circuit is configured to slice the data packet from the service port based on the byte length M to obtain a data slice, send a slice frame to the framing device and slice description information associated with the slice frame, wherein the slice frame comprises a preset number of data slices, and the slice description information comprises information for describing the end slice of the data packet; The framing device is configured to fill slice frames from the slicing devices and the slice description information associated with the slice frames into a flow control unit Flit, and send the Flit to the deframer; The deframer is configured to determine slice frames belonging to the same service port from the Flit, and send the slice frames and the slice description information associated with the slice frames to a packet circuit corresponding to the service port; the packet assembling circuit is configured to splice the data slices belonging to the same data packet in the slice frame and output the data packet based on the slice description information. In a possible manner, the slice description information further comprises validity indication information, wherein the validity indication information is used for indicating validity of the data slice in the slice frame. In one possible way, the slice description information includes a classification identifier; The classification identification indicates a type of the slice frame based on a validity and homology of the data slice in the slice frame. In a possible manner, the slice description information further comprises an end identifier and a byte length identifier, wherein the end identifier is used for indicating a data packet end slice in the slice frame, and the byte length identifier is used for indicating whether the byte length of the data packet end slice reaches M. In one possible manner, the slicing circuit includes: a slice storage unit, a first MUX group, a first FIFO group, and a second MUX group; The slice storage unit is configured to store data slices segmented based on spliced data, wherein the data slices comprise a first data slice and a second data slice, the first data slice comprises a data slice with a byte length of M at the end of a non-data packet or a data slice with a byte length of less than or equal to M at the end of the data packet, and the second data slice comprises a data slice with a byte length of less than M at the end of the non-data packet; The first MUX group is configured to write the first data slice to the first FIFO group in cycles; The second MUX group is co