CN-121442690-B - Semiconductor structure and preparation method thereof

CN121442690BCN 121442690 BCN121442690 BCN 121442690BCN-121442690-B

Abstract

The disclosure provides a semiconductor structure and a preparation method of the semiconductor structure, and relates to the technical field of semiconductors. The preparation method of the semiconductor structure comprises the steps of providing a substrate, stacking the substrate along a first direction to form a stacked structure, forming an opening on at least one side of the active layer along a second direction, penetrating the stacked structure and exposing the substrate, filling a metal material in the opening and enabling the metal material and the exposed substrate to form a first protection layer, and removing the metal material, wherein the first direction intersects with the upper surface of the substrate and is perpendicular to the second direction. When the opening is filled with the metal material, the metal material can be adsorbed on the upper surface of the exposed substrate and reacts with the substrate to form a first protection layer in a self-alignment mode, deposition and etching process steps are omitted, process cost is saved, the first protection layer is metal silicide, the first protection layer can resist wet etching solution, the substrate is prevented from being damaged by the wet etching solution, and the effect of protecting the substrate is achieved.

Inventors

SUN PENGCHAO
Zhong Baojian
ZHANG MING
FENG WEI
SUN ZHENG
LIU MINGYUAN

Assignees

长鑫科技集团股份有限公司

Dates

Publication Date: 20260508
Application Date: 20251231

Claims (8)

1. A method of fabricating a semiconductor structure, comprising the steps of: Providing a substrate; stacking the substrates along a first direction to form a stacking structure, wherein the stacking structure comprises an active layer; Forming an opening on at least one side of the active layer along a second direction, wherein the opening penetrates through the stacked structure and exposes the substrate; Filling a metal material in the opening, and forming a first protection layer by the metal material and the exposed substrate; Removing the metal material; The stacked structure further comprises a bottom dielectric layer and an interlayer dielectric layer, wherein the bottom dielectric layer is positioned on the upper surface of the substrate, the interlayer dielectric layer is positioned between the bottom dielectric layer and the active layer, and the opening penetrates through the bottom dielectric layer; after exposing the substrate, further comprising the steps of: removing the part of the bottom dielectric layer surrounding the opening to form a gap between the substrate and the interlayer dielectric layer, wherein the gap is annularly arranged around the opening and communicated with the opening; When the opening is filled with a metal material, the metal material can be filled in the gap and contacted with the substrate to form a second protective layer.
2. The method of claim 1, wherein the metallic material comprises metallic titanium, and the first protective layer and the second protective layer comprise titanium silicide.
3. The method of claim 1, wherein the first protective layer and the second protective layer are formed using a high temperature annealing process.
4. A method of fabricating a semiconductor structure according to any one of claims 1 to 3, wherein the depth of the opening in the first direction is greater than the height of the stacked structure in the first direction.
5. A semiconductor structure, comprising: A substrate; The stacking structure is stacked and arranged on the substrate along a first direction and comprises an active layer, at least one side of the active layer along a second direction is provided with a filling part, and the filling part penetrates through the stacking structure; A first protection layer disposed between the filling portion and the substrate and in contact with the substrate, the first protection layer including a metal silicide; The stacked structure further comprises a bottom dielectric layer and an interlayer dielectric layer, wherein the bottom dielectric layer is positioned on the upper surface of the substrate, the interlayer dielectric layer is positioned between the bottom dielectric layer and the active layer, and the filling part penetrates through the bottom dielectric layer; The semiconductor structure further comprises a second protection layer, wherein the second protection layer is located between the substrate and the interlayer dielectric layer, and the second protection layer is arranged around the filling part in a surrounding mode and is arranged between the first protection layer and the bottom dielectric layer.
6. The semiconductor structure of claim 5, wherein the second protective layer comprises titanium silicide.
7. The semiconductor structure of claim 5, wherein the first protective layer and the second protective layer are an integrally formed structure.
8. The semiconductor structure of any of claims 5-7, wherein a lower surface of the filling portion is lower than an upper surface of the substrate in the first direction.

Description

Semiconductor structure and preparation method thereof Technical Field The disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Dynamic Random Access Memory (DRAM) is used as a core device in the field of semiconductor memory, and is widely applied to various electronic devices such as computers, servers, mobile terminals and the like. The existing memory cells are stacked in multiple layers along the direction perpendicular to the substrate, and the integration level of the memory cells can be improved on the premise of not expanding the plane area. In order to realize vertical interconnection of the memory cells, dielectric layers in the stacked structure are required to be selectively etched through a side-pulling process. However, in the process of silicon side picking, the etching solution can directly contact the exposed surface of the substrate, and the etching solution can erode the substrate, so that lattice damage and surface defects of the substrate occur, and peeling or microcracking of the interface between the substrate and the stacked structure is caused, thereby influencing the reliability of the semiconductor structure. It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art. Disclosure of Invention The disclosure provides a semiconductor structure and a preparation method thereof, which reduce substrate damage and realize substrate protection. Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the disclosure. According to one aspect of the disclosure, a method for manufacturing a semiconductor structure is provided, and the method comprises the steps of providing a substrate, stacking the substrate along a first direction to form a stacked structure, forming an opening on at least one side of the active layer along a second direction, penetrating the stacked structure and exposing the substrate, filling a metal material in the opening, enabling the metal material and the exposed substrate to form a first protection layer, and removing the metal material, wherein the first direction intersects with the upper surface of the substrate and is perpendicular to the second direction. In some embodiments, the stacked structure further comprises a bottom dielectric layer and an interlayer dielectric layer, wherein the bottom dielectric layer is positioned on the upper surface of the substrate, the interlayer dielectric layer is positioned between the bottom dielectric layer and the active layer, the opening penetrates through the bottom dielectric layer, after the substrate is exposed, a gap is formed between the substrate and the interlayer dielectric layer by removing the part, surrounding the opening, of the bottom dielectric layer, the gap is arranged around the opening and is communicated with the opening, and when the opening is filled with a metal material, the metal material can be filled in the gap and is contacted with the substrate to form a second protection layer. In some embodiments, the metal material comprises metallic titanium, and the first protective layer and the second protective layer comprise titanium silicide. In some of these embodiments, the first and second protective layers are formed using a high temperature annealing process. In some of these embodiments, the depth of the opening in the first direction is greater than the height of the stacked structure in the first direction. According to a second aspect of the invention, the embodiment of the invention further provides a semiconductor structure, which comprises a substrate, a stacked structure and a first protection layer, wherein the stacked structure is stacked on the substrate along a first direction, the stacked structure comprises an active layer, at least one side of the active layer along a second direction is provided with a filling part, the filling part penetrates through the stacked structure, the first protection layer is arranged between the filling part and the substrate and is in contact with the substrate, the first protection layer comprises metal silicide, and the first direction intersects with the upper surface of the substrate and is perpendicular to the second direction. In some embodiments, the stacked structure further comprises a bottom dielectric layer and an interlayer dielectric layer, wherein the bottom dielectric layer is positioned on the upper surface of the substrate, the interlayer dielectric layer is positioned between the bottom dielectric layer and the active layer, the filling part penetrates through the bottom dielectric layer, the se