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CN-121454139-B - Clock frequency measurement method, device, equipment and computer readable storage medium

CN121454139BCN 121454139 BCN121454139 BCN 121454139BCN-121454139-B

Abstract

The application relates to the technical field of clock frequency measurement, in particular to a clock frequency measurement method, a device, equipment and a computer readable storage medium, wherein the method is applied to a programmable logic chip, and the programmable logic chip is respectively connected with a clock source, a time service module and a temperature acquisition module, acquires a clock signal to be measured of the clock source and a second pulse signal of the time service module, and performs frequency multiplication processing according to the clock signal to be measured to obtain a frequency multiplication clock signal; the method comprises the steps of determining a time original code value according to an edge time interval between a second pulse signal and a frequency multiplication clock signal, carrying out time calibration on the time original code value according to real-time temperature data provided by a temperature acquisition module to obtain fine time data corresponding to the time original code value, and determining the clock frequency of the clock signal to be measured according to the fine time data and a coarse count value of the frequency multiplication clock signal in a signal period of the second pulse signal so as to improve the accuracy of clock frequency measurement on the premise of not increasing hardware resource expenditure.

Inventors

  • ZHENG JIAJUN

Assignees

  • 合肥中科采象科技有限公司

Dates

Publication Date
20260508
Application Date
20251231

Claims (9)

  1. 1. The clock frequency measuring method is characterized by being applied to a programmable logic chip, wherein the programmable logic chip is respectively connected with a clock source, a time service module and a temperature acquisition module, and the clock frequency measuring method comprises the following steps: Acquiring a clock signal to be detected of the clock source and a second pulse signal of the time service module, and performing frequency multiplication according to the clock signal to be detected to obtain a frequency multiplication clock signal; determining a time original code value according to an edge time interval between the second pulse signal and the frequency multiplication clock signal; Performing time calibration on the time original code value according to the real-time temperature data provided by the temperature acquisition module to obtain fine time data corresponding to the time original code value; Determining a clock frequency of the clock signal to be measured according to the fine time data and a coarse count value of the frequency multiplication clock signal in a signal period of the second pulse signal, wherein the programmable logic chip comprises a coarse count module and a frequency calculation module, the frequency calculation module is respectively connected with the coarse count module and a temperature calibration coding module in the programmable logic chip, and the step of determining the clock frequency of the clock signal to be measured according to the fine time data and the coarse count value of the frequency multiplication clock signal in the signal period of the second pulse signal comprises the following steps: in the signal period from the rising edge of each second pulse signal to the rising edge of the next second pulse signal, the coarse counting module counts the rising edge of the frequency doubling clock signal to obtain a coarse counting value of the frequency doubling clock signal, the frequency calculating module is enabled to determine the clock frequency of the clock signal to be measured according to the coarse counting value and the fine time data, The first fine time data and the second fine time data represent the fine time from the rising edge of two adjacent second pulse signals to the rising edge of the frequency multiplication clock signal nearest to the rising edge of the second pulse signal, the first coarse count value and the second coarse count value correspond to the corresponding rising edge count value of the frequency multiplication clock signal in the signal period of two adjacent second pulse signals, and the frequency calculation module is configured to calculate the first fine time data, the second fine time data, the first coarse count value and the second coarse count value according to a preset clock frequency calculation algorithm to obtain the clock frequency of the clock signal to be measured; The expression of the clock frequency calculation algorithm is as follows: representing a first coarse count value; Representing a second coarse count value; representing single period time of the frequency multiplication clock signal, wherein the preset time threshold value is 1 second; representing the clock frequency of the clock signal to be measured, Representing the frequency multiplication coefficient of the clock signal to be measured; Representing first fine time data; representing second fine time data.
  2. 2. The method of claim 1, wherein the programmable logic chip includes a frequency multiplication module, the frequency multiplication module is connected to the clock source, and the step of performing frequency multiplication processing according to the clock signal to be measured to obtain a frequency-multiplied clock signal includes: When the frequency multiplication module receives the clock signal to be detected of the clock source, the frequency multiplication module carries out frequency multiplication processing on the clock signal to be detected to obtain a frequency multiplication clock signal.
  3. 3. The method of claim 2, wherein the programmable logic chip includes a short delay chain module, the short delay chain module is respectively connected with the frequency multiplication module and the time service module, and the step of determining the time source code value according to the edge time interval between the second pulse signal and the frequency multiplication clock signal includes: activating the short delay chain module by taking the rising edge of the second pulse signal as a starting signal, and determining the first rising edge of the frequency multiplication clock signal appearing after the starting signal as a stop reference signal through the activated short delay chain module; And measuring the edge time interval between the starting signal and the stopping reference signal through an activated short delay chain module to obtain a time original code value of the edge time interval.
  4. 4. The method for measuring clock frequency as recited in claim 3 wherein said programmable logic chip comprises a temperature monitoring module and a temperature calibration coding module, said temperature monitoring module is respectively connected with said temperature calibration coding module and said temperature acquisition module, said temperature calibration coding module is connected with said short delay chain module, said step of time calibrating said time origin code value according to real-time temperature data provided by said temperature acquisition module, obtaining fine time data corresponding to said time origin code value comprises: Acquiring real-time temperature data sent by the temperature acquisition module through the temperature monitoring module, and carrying out data preprocessing according to the real-time temperature data to obtain a real-time temperature value; reading a preset temperature-code value calibration coefficient mapping table through the temperature calibration coding module, and acquiring a target code value calibration coefficient corresponding to the real-time temperature value from the temperature-code value calibration coefficient mapping table; and obtaining fine time data according to the product value between the target code value calibration coefficient and the time original code value.
  5. 5. The method of claim 4, wherein the step of enabling the frequency calculation module to determine the clock frequency of the clock signal under test based on the coarse count value and the fine time data comprises: determining each piece of fine time data as first fine time data by the frequency calculation module, and taking the next fine time data adjacent to the first fine time data as second fine time data; Determining, by the frequency calculation module, that a coarse count value of the coarse count module on the frequency-multiplied clock signal in each signal period is a first coarse count value, and determining that a coarse count value of the coarse count module in a next signal period adjacent to each signal period is a second coarse count value; and determining the clock frequency of the clock signal to be measured according to the first fine time data, the second fine time data, the first coarse count value and the second coarse count value.
  6. 6. The method of claim 5, wherein the step of determining the clock frequency of the clock signal under test based on the first fine time data, the second fine time data, the first coarse count value, and the second coarse count value comprises: after the second fine time data and the first fine time data are differenced, overlapping the second fine time data and a preset time threshold value to obtain time overlapping data, and determining a coarse count difference value between the second coarse count value and the first coarse count value; And determining single period time of the frequency multiplication clock signal according to the proportion data between the time superposition data and the coarse count difference value, and obtaining the clock frequency of the clock signal to be tested according to the single period time and the frequency multiplication coefficient of the clock signal to be tested.
  7. 7. A clock frequency measurement device, the clock frequency measurement device comprising: The acquisition module is used for acquiring a clock signal to be detected of a clock source and a second pulse signal of the time service module, and performing frequency multiplication processing according to the clock signal to be detected to obtain a frequency multiplication clock signal; the code value determining module is used for determining a time original code value according to the edge time interval between the second pulse signal and the frequency multiplication clock signal; The calibration module is used for carrying out time calibration on the time original code value according to the real-time temperature data provided by the temperature acquisition module to obtain fine time data corresponding to the time original code value; The frequency determining module is configured to determine a clock frequency of the clock signal to be measured according to the fine time data and a coarse count value of the frequency multiplication clock signal in a signal period of the second pulse signal, where the programmable logic chip includes a coarse count module and a frequency calculating module, the frequency calculating module is respectively connected with the coarse count module and a temperature calibration coding module in the programmable logic chip, and the step of determining the clock frequency of the clock signal to be measured according to the fine time data and the coarse count value of the frequency multiplication clock signal in the signal period of the second pulse signal includes: in the signal period from the rising edge of each second pulse signal to the rising edge of the next second pulse signal, the coarse counting module counts the rising edge of the frequency doubling clock signal to obtain a coarse counting value of the frequency doubling clock signal, the frequency calculating module is enabled to determine the clock frequency of the clock signal to be measured according to the coarse counting value and the fine time data, The first fine time data and the second fine time data represent the fine time from the rising edge of two adjacent second pulse signals to the rising edge of the frequency multiplication clock signal nearest to the rising edge of the second pulse signal, the first coarse count value and the second coarse count value correspond to the corresponding rising edge count value of the frequency multiplication clock signal in the signal period of two adjacent second pulse signals, and the frequency calculation module is configured to calculate the first fine time data, the second fine time data, the first coarse count value and the second coarse count value according to a preset clock frequency calculation algorithm to obtain the clock frequency of the clock signal to be measured; The expression of the clock frequency calculation algorithm is as follows: representing a first coarse count value; Representing a second coarse count value; representing single period time of the frequency multiplication clock signal, wherein the preset time threshold value is 1 second; representing the clock frequency of the clock signal to be measured, Representing the frequency multiplication coefficient of the clock signal to be measured; Representing first fine time data; representing second fine time data.
  8. 8. A clock frequency measurement device comprising a memory, a processor and a clock frequency measurement program stored on the memory and executable on the processor, the processor implementing the steps of the clock frequency measurement method according to any one of claims 1 to 6 when the processor executes the clock frequency measurement program.
  9. 9. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a clock frequency measurement program which, when executed by a processor, implements the steps of the clock frequency measurement method according to any one of claims 1 to 6.

Description

Clock frequency measurement method, device, equipment and computer readable storage medium Technical Field The present application relates to the field of clock frequency measurement technologies, and in particular, to a method, an apparatus, a device, and a computer readable storage medium for measuring clock frequency. Background With the continuous deep application of the high-precision clock frequency measurement technology in the fields of particle physics, astronomical observation, mobile communication, navigation positioning and the like, a user puts higher requirements on the precision, stability and real-time calibration capability of clock frequency measurement. Currently, high-precision clock frequency measurement schemes in the industry commonly employ TDC (Time-to-Digital Converter ) based techniques to calculate the clock frequency by accurately measuring the cumulative Time interval of multiple cycles of the clock signal. However, the scheme based on the TDC still has significant technical defects in practical application, for example, a lengthy delay chain is required to be constructed to realize ps (picosecond) level measurement precision, so that the FPGA (Field-Programmable gate array) logic resource consumption is large and the cost is high, meanwhile, the unit delay time of the delay chain is easily influenced by ambient temperature drift, measurement errors changing along with time are introduced, the accuracy and the stability of long-term measurement are seriously damaged, in addition, a system integrating the FPGA lacks real-time online temperature self-calibration capability, and the periodic off-line calibration and manual compensation are required to be carried out by depending on external equipment, so that the operation is complicated, the maintenance cost is high, and the real-time error generated due to temperature change in the work cannot be dynamically corrected, so that the actual measurement accuracy is reduced, and the requirement of a high-reliability application scene is difficult to be satisfied. Therefore, how to improve the accuracy of clock frequency measurement without increasing the hardware resource overhead is a technical problem to be solved at present. Disclosure of Invention The application mainly aims to provide a clock frequency measurement method, a device, equipment and a computer readable storage medium, aiming at improving the accuracy of clock frequency measurement on the premise of not increasing the cost of hardware resources. In order to achieve the above object, the present application provides a clock frequency measurement method, which is applied to a programmable logic chip, wherein the programmable logic chip is respectively connected with a clock source, a time service module and a temperature acquisition module, and the clock frequency measurement method includes: Acquiring a clock signal to be detected of the clock source and a second pulse signal of the time service module, and performing frequency multiplication according to the clock signal to be detected to obtain a frequency multiplication clock signal; determining a time original code value according to an edge time interval between the second pulse signal and the frequency multiplication clock signal; Performing time calibration on the time original code value according to the real-time temperature data provided by the temperature acquisition module to obtain fine time data corresponding to the time original code value; And determining the clock frequency of the clock signal to be tested according to the fine time data and the coarse count value of the frequency multiplication clock signal in the signal period of the second pulse signal. In an embodiment, the programmable logic chip includes a frequency multiplication module, the frequency multiplication module is connected with the clock source, and the step of obtaining the frequency multiplication clock signal by performing frequency multiplication processing according to the clock signal to be tested includes: When the frequency multiplication module receives the clock signal to be detected of the clock source, the frequency multiplication module carries out frequency multiplication processing on the clock signal to be detected to obtain a frequency multiplication clock signal. In an embodiment, the programmable logic chip includes a short delay chain module, the short delay chain module is respectively connected with the frequency multiplication module and the time service module, and the step of determining the time original code value according to the edge time interval between the second pulse signal and the frequency multiplication clock signal includes: activating the short delay chain module by taking the rising edge of the second pulse signal as a starting signal, and determining the first rising edge of the frequency multiplication clock signal appearing after the starting signal as a stop reference signal through the a