CN-121463868-B - Wafer bonding method and compound semiconductor device

CN121463868BCN 121463868 BCN121463868 BCN 121463868BCN-121463868-B

Abstract

The application relates to the technical field of semiconductors, in particular to a wafer bonding method and a compound semiconductor device, wherein the wafer bonding method comprises the steps of forming a first electrode and a first enclosing wall on a silicon-based wafer, wherein the first enclosing wall is used for isolating the first electrode; forming a second electrode and a second enclosing wall on the compound semiconductor wafer, wherein the second enclosing wall is used for isolating the second electrode, implanting metal balls on the first electrode and/or the second electrode, reversely buckling the compound semiconductor wafer on the silicon-based wafer, bonding the compound semiconductor wafer and the silicon-based wafer through the implanted metal balls, limiting diffusion areas of the implanted metal balls through the first enclosing wall and the second enclosing wall in the bonding process to obtain an initial bonding wafer, and performing bottom filling and thinning treatment on the initial bonding wafer to obtain the target bonding wafer. The application has the advantages of high packaging integration level, low packaging process difficulty and cost, strong reliability and strong mass production performance.

Inventors

HE YUAN
ZHU XIN

Assignees

苏州矩阵光电有限公司

Dates

Publication Date: 20260512
Application Date: 20251231

Claims (4)

1. A method of wafer bonding, the method comprising: Providing a silicon-based wafer and a compound semiconductor wafer; forming a first electrode and a first enclosing wall on the silicon-based wafer, wherein the first enclosing wall is used for isolating the first electrode, forming a second electrode and a second enclosing wall on the compound semiconductor wafer, wherein the second enclosing wall is used for isolating the second electrode, the distance between two adjacent enclosing walls is larger than 10um, each two adjacent enclosing walls comprises two adjacent first enclosing walls and two adjacent second enclosing walls, the first enclosing wall and the second enclosing wall are cylindrical enclosing walls, the inner diameters of the first enclosing wall and the second enclosing wall are 60um-100um, the outer diameters of the first enclosing wall and the second enclosing wall are 100um-150um, and the heights of the first enclosing wall and the second enclosing wall are 3um-15um; Implanting metal balls on the first electrode and/or the second electrode, wherein the diameter of each metal ball is 50-80 um, the height of each metal ball is 5-20 um, the distance between the outer surface of each metal ball and the side wall of the corresponding enclosing wall is more than 3um, and the corresponding enclosing wall is an enclosing wall for isolating the electrode implanted by the metal ball; The compound semiconductor wafer is placed on the silicon-based wafer in a reverse buckling mode, so that the compound semiconductor wafer and the silicon-based wafer are bonded through the implanted metal balls, and diffusion areas of the implanted metal balls are limited through the first enclosing wall and the second enclosing wall in the bonding process, and an initial bonding wafer is obtained; in the bonding process of the compound semiconductor wafer and the silicon-based wafer through the implanted metal balls, the metal balls are flattened and filled in the grooves between the compound semiconductor wafer and the silicon-based wafer, and meanwhile, excessive metal overflows, wherein the range of overflowed metal is smaller than a target value, the target value is the sum of the outer diameter of the corresponding enclosing wall and a target distance, and the target distance is half of the distance between two adjacent enclosing walls; And performing thinning treatment on the compound semiconductor wafer substrate in the filled bonding wafer by using a physical grinding or gas phase etching or chemical solution etching method to obtain a target bonding wafer, wherein the underfill is used for isolating particles generated in the thinning treatment and improving the bonding force between the silicon-based wafer and the compound semiconductor wafer, and the thickness of the target bonding wafer is 20um-100um.
2. The wafer bonding method of claim 1, wherein the number of metal balls matches the number of implanted electrodes, the metal balls being placed in a central location of the implanted electrodes.
3. The wafer bonding method according to claim 1 or 2, wherein after the performing the underfill and thinning process on the initially bonded wafer to obtain a target bonded wafer, the method further comprises: And carrying out planarization treatment and electrode opening packaging treatment on the target bonding wafer by using photosensitive protective adhesive.
4. A compound semiconductor device characterized in that the compound semiconductor device includes a target bonded wafer formed using the wafer bonding method according to any one of claims 1 to 3.

Description

Wafer bonding method and compound semiconductor device Technical Field The present application relates to the field of semiconductor manufacturing, and in particular, to a wafer bonding method and a compound semiconductor device. Background In the related art, the encapsulation between a silicon-based wafer (Si-based IC) and a compound semiconductor wafer is generally performed by connecting the Si-based IC and the compound semiconductor by bonding wires, connecting different chips by a through-silicon via (TSV via), directly bonding the silicon-based wafer and the compound epitaxial wafer, and performing wafer processing after etching the epitaxial wafer substrate. However, the bonding wires are used for connecting the Si-based IC and the compound semiconductor, so that the bonding wires are large in occupied area, gold wires and other consumable materials are used more, the integration level is low, the TSV perforation mode is high in process difficulty, high in cost and low in reliability, the direct bonding mode has high requirements on the surface evenness of the wafer, various high-temperature processes are designed in the subsequent wafer process processing, the problem that materials are damaged due to mismatching of thermal expansion coefficients is easy to occur, and the mass productivity is low. Therefore, it is particularly important to provide a wafer bonding method and a compound semiconductor device capable of realizing high packaging integration, low packaging process difficulty and cost, high reliability and high mass productivity. Disclosure of Invention The present application provides a wafer bonding method and a compound semiconductor device to solve at least the above problems in the related art. In order to solve the technical problems, the technical scheme of the application is as follows: in one aspect, an embodiment of the present application provides a wafer bonding method, including: Providing a silicon-based wafer and a compound semiconductor wafer; Forming a first electrode and a first enclosing wall on the silicon-based wafer, wherein the first enclosing wall is used for isolating the first electrode; forming a second electrode and a second enclosure on the compound semiconductor wafer, the second enclosure being for isolating the second electrode; implanting metal balls on the first electrode and/or the second electrode; The compound semiconductor wafer is placed on the silicon-based wafer in a reverse buckling mode, so that the compound semiconductor wafer and the silicon-based wafer are bonded through the implanted metal balls, and diffusion areas of the implanted metal balls are limited through the first enclosing wall and the second enclosing wall in the bonding process, and an initial bonding wafer is obtained; and performing bottom filling and thinning treatment on the initial bonding wafer to obtain the target bonding wafer. In an alternative embodiment, the first enclosing wall and the second enclosing wall are both cylindrical enclosing walls, the inner diameters of the first enclosing wall and the second enclosing wall are 60um-100um, the outer diameters of the first enclosing wall and the second enclosing wall are 100um-150um, the heights of the first enclosing wall and the second enclosing wall are 3um-15um, the distance between two adjacent enclosing walls is greater than 10um, and the two adjacent enclosing walls comprise two adjacent first enclosing walls and two adjacent second enclosing walls. In an alternative embodiment, the diameter of the metal ball is 50um-80um, the height of the metal ball is 5um-20um, the distance between the outer surface of the metal ball and the side wall of the corresponding enclosing wall is greater than 3um, and the corresponding enclosing wall is an enclosing wall for isolating the electrode implanted by the metal ball. In an alternative embodiment, during the bonding of the compound semiconductor wafer and the silicon-based wafer by the implanted metal balls, the metal balls are flattened to fill the grooves between the compound semiconductor wafer and the silicon-based wafer, and the excessive metal overflows; the range of overflowed metal meets the preset condition, and the preset condition is determined based on the outer diameter of the corresponding enclosing wall and the distance between two adjacent enclosing walls. In an alternative embodiment, the range of the overflowed metal is less than a target value, the target value being the sum of the outer diameter of the corresponding enclosure and a target distance that is half the distance between two adjacent enclosures. In an alternative embodiment, the number of metal balls matches the number of implanted electrodes, the metal balls being placed in the center of the implanted electrodes. In an alternative embodiment, the performing the underfill and thinning on the initially bonded wafer to obtain the target bonded wafer includes: Filling underfill between the initial bo