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CN-121478321-B - FPGA three-segment finite state machine identification and extraction method and device based on RTL codes

CN121478321BCN 121478321 BCN121478321 BCN 121478321BCN-121478321-B

Abstract

Acquiring an RTL code module of an FPGA three-section finite state machine to be identified and extracted, searching and extracting a time sequence process and a combination process with internal signal update, and searching and extracting a process or a logic fragment which takes the internal signal as a condition signal and does not perform assignment operation on the internal signal under a condition branch; judging whether 3 processes exist or whether 2 processes and 1 logic segment exist or not to meet the logic relation of the three-section finite state machine, if so, judging that the three-section finite state machine exists in the current RTL code module. The method can directly identify and extract the three-section finite state machine of the FPGA through the RTL code, and can simultaneously meet the requirements of checking the correctness of the design of the three-section finite state machine and the compliance of the coding rules.

Inventors

  • YE WEISONG

Assignees

  • 深远华创(南京)信息科技有限公司

Dates

Publication Date
20260512
Application Date
20260108

Claims (7)

  1. 1. The method for identifying and extracting the FPGA three-section finite state machine based on the RTL code is characterized by comprising the following steps of: step 1, acquiring an RTL code module of an FPGA three-section finite state machine to be identified and extracted; step 2, searching and extracting a time sequence process with internal signal update in the RTL code module, wherein the time sequence process is a process which must be executed by clock edge triggering logic and satisfies that all logic operation results are uniformly updated when the next clock edge arrives; Step 3, searching and extracting a combination process of internal signal update in the RTL code module, wherein the combination process is a process of triggering logic execution along with the level change of an input signal without a clock signal, and meets the condition that all logic operation results are updated in real time along with the change of a triggering condition; Step 4, searching and extracting a process or a logic fragment which takes an internal signal as a conditional signal and performs assignment operation on the internal signal does not exist in the RTL code module under a conditional branch; Step 5, analyzing all the processes and logic fragments extracted in the step 2 to the step 4, and judging that a three-section finite state machine exists in the current RTL code module if 3 processes exist or if 2 processes exist and 1 logic fragment satisfy the logic relation of the three-section finite state machine, wherein the method comprises the following steps: Step 51, analyzing all time sequence processes extracted in the step 2, and identifying a process which has the characteristics that a signal A and a signal B exist and the signal A is positioned on the left side of an assignment statement assignment symbol and the signal B is positioned on the right side of the assignment statement assignment symbol; Step 52, analyzing all the combined processes extracted in the step 3, and identifying a process which meets the CASE or IF conditional statement containing the signal A in the step 51 as a conditional signal, wherein an assignment symbol exists under each conditional branch, the left side of the assignment symbol is the signal B in the step 51, and the right side of the assignment symbol is the assignment statement of the vector signal or the enumeration signal; Step 53, analyzing all the processes or logic fragments extracted in step 4, identifying a process or logic fragment which satisfies a CASE or IF conditional statement containing the signal a in step 51 as a conditional signal, and under each conditional branch there is no signal a and no signal B in step 51; step 54, if and only if the conditions in step 51, step 52 and step 53 are all satisfied, the three-section finite state machine logic relationship is satisfied, and the existence of the three-section finite state machine in the current RTL code module is determined; and 6, searching all the conditional expressions, state assignment relations and all the state signals corresponding to the update of the internal signals in the combined process extracted in the step 5, taking all the state signals as nodes, taking the assignment relations as the jump flow among the nodes, and constructing and obtaining a three-section finite state machine state jump diagram by taking the conditional expressions as jump conditions, wherein the method comprises the following steps of: step 61, analyzing the CASE or IF conditional statement in the combined process obtained in step 52, extracting a conditional expression from each conditional control branch, taking a signal on the right of an assignment symbol of the assignment statement under each conditional control branch as a state signal, taking the flow direction relation of the right end of the assignment symbol flowing to the left end as each state jump flow direction, and recording the conditional expression, the state signal and the state jump flow direction respectively; And step 62, using each state signal extracted in the step 61 as a node, using a conditional expression as each state signal jump condition, and constructing a three-section finite state machine state jump diagram between each node according to each state signal jump flow direction.
  2. 2. The method for identifying and extracting the three-segment finite state machine of the FPGA based on the RTL code according to claim 1, wherein in step 2, a time sequence process of updating an internal signal in the RTL code module is searched and extracted, and the method comprises the steps of: Step 21, analyzing an RTL code module, and identifying all processes containing clock signals in a sensitive list; And 22, screening all processes which execute assignment operation through an assignment statement from all time sequence processes identified in the step 21, wherein the assignment statement satisfies that the left end and the right end of the assignment symbol only contain one signal, the signal at the left end is marked as A, and the signal at the right end is marked as B.
  3. 3. The method for identifying and extracting the three-segment finite state machine of the FPGA based on the RTL code according to claim 2, wherein step 3, searching and extracting a combination process of an internal signal update existing in the RTL code module, includes: Step 31, analyzing an RTL code module, and identifying all processes which do not contain clock signals in a sensitive list; and step 32, screening out the processes with CASE or IF conditional sentences from all the processes identified in the step 31, wherein the CASE or IF conditional sentences meet that each conditional branch has an assignment sentence, the left end and the right end of the assignment sentence are signals, and the left end is an internal signal and is marked as C.
  4. 4. An FPGA three-segment finite state machine recognition and extraction device based on RTL codes, which is characterized in that the device is used for implementing the method of any one of claims 1 to 3, and the device comprises: the code acquisition module is used for acquiring an RTL code module of the FPGA three-section finite state machine to be identified and extracted; The feature recognition module is used for searching and extracting a time sequence process of the internal signal update in the RTL code module, searching and extracting a combined process of the internal signal update in the RTL code module, and searching and extracting a process or a logic fragment which takes the internal signal as a condition signal and does not perform assignment operation on the internal signal under a condition branch in the RTL code module; The state machine confirming module is used for confirming whether 3 processes exist or whether 2 processes exist and a logic segment meets the logic relation of the three-section finite state machine, and if so, judging that the three-section finite state machine exists in the current RTL code module; and the state jump diagram construction module is used for searching all the conditional expressions, state assignment relations and all the state signals corresponding to the internal signal update from the combined process extracted by the state machine confirmation module, taking all the state signals as nodes, taking the assignment relations as jump flow directions among the nodes, and constructing and obtaining the three-section finite state machine state jump diagram by taking the conditional expressions as jump conditions.
  5. 5. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the method of any of claims 1-3 when executing the program.
  6. 6. A computer readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the method of any of claims 1-3.
  7. 7. A computer program product comprising a computer program, characterized in that the computer program, when executed by a processor, implements the method of any of claims 1-3.

Description

FPGA three-segment finite state machine identification and extraction method and device based on RTL codes Technical Field The invention belongs to the technical field of electronic design automation, and particularly relates to an identification and extraction method and device of an FPGA three-segment finite state machine based on an RTL code. Background The FPGA is widely used by virtue of its strong reconfigurability, low latency, real-time performance and parallel computing capability, wherein the FSM (FINITE STATE MACHINE ) is a design mode commonly used in FPGA development, which can improve the readability, maintainability and reliability of codes, and can be widely used in the fields of control systems, communication protocols, data processing, timing control and the like. Therefore, the correctness of FSM design is very important, and almost all safety critical fields require a comprehensive inspection of FSM for design defects, and at the same time, the implementation of FSM must meet industry code rules. Currently, FSM has 3 design modes of one-segment type, two-segment type and three-segment type, wherein three-segment type can effectively eliminate the hidden troubles of instability and burrs of combinational logic compared with other 2 design modes, so that FSM is most widely applied in the safety critical field, but at the same time, three-segment type is also the most complex one in FSM design. To check the correctness of the FSM and its compliance with the encoding rules, a correctness and normalization check needs to be performed on the design of the FSM, which requires accurate identification and extraction of the FSM in the RTL code. However, since the current FPGA design is basically based on RTL codes, and the syntax of the RTL codes is very flexible, there is no inherent limitation on the FSM design, and thus there is no direct means for accurately identifying and extracting FSMs, especially for three-segment FSMs. The prior art has many researches on FSM identification and extraction in FPGA, but no effective extraction and identification method is provided, and patent CN112036104A discloses a finite state machine identification and extraction method based on RTL netlist. However, the method has many limiting conditions, firstly, the method needs to complete all designs of the FPGA and compile and synthesize to obtain an RTL netlist, and the efficiency of the method is very low because the FPGA synthesis process is very time-consuming, secondly, the method is based on the RTL netlist, so that the extracted FSM cannot be directly mapped to a corresponding RTL code and cannot support the inspection of the FSM coding rule, and finally, the method is not suitable for the three-section FSM and cannot meet the application requirements of the safety key field. In order to meet the requirements of checking the correctness and coding rule compliance of the FSM design, an efficient technical means is urgently required to be provided, the FSM in the FPGA design can be directly identified and extracted based on the RTL code without depending on the RTL netlist of the FPGA, and particularly, the complex three-section FSM can be extracted and identified, so that the application requirements of the safety key field are met, and the reliability and quality of the FSM design in the FPGA design are improved. Disclosure of Invention Aiming at the problems that the existing method for identifying and extracting the FPGA finite state machine is too limited, has insufficient practicability and is not suitable for a three-section type FSM, the invention provides the method and the device for identifying and extracting the FPGA three-section type finite state machine based on the RTL code, which can directly identify and extract the three-section type finite state machine of the FPGA through the RTL code and can simultaneously meet the requirements of checking the correctness of the design of the three-section type finite state machine and the compliance of coding rules. The technical scheme for realizing the purpose of the invention is that the method for identifying and extracting the FPGA three-section finite state machine based on the RTL code comprises the following steps: step 1, acquiring an RTL code module of an FPGA three-section finite state machine to be identified and extracted; step 2, searching and extracting a time sequence process with internal signal update in the RTL code module, wherein the time sequence process is a process which must be executed by clock edge triggering logic and satisfies that all logic operation results are uniformly updated when the next clock edge arrives; Step 3, searching and extracting a combination process of internal signal update in the RTL code module, wherein the combination process is a process of triggering logic execution along with the level change of an input signal without a clock signal, and meets the condition that all logic operation results are up