CN-121478345-B - Programmable logic device dynamic register configuration device and control method thereof

CN121478345BCN 121478345 BCN121478345 BCN 121478345BCN-121478345-B

Abstract

The present disclosure provides a programmable logic device dynamic register configuration apparatus and a control method thereof. The programmable logic device dynamic register configuration device comprises an external controller, a main controller, at least one multiplexing module and one or more sub-controllers, wherein the external controller is used for providing configuration instructions and configuration data, the main controller is used for receiving and analyzing the configuration data, generating gating signals and reconstructing data packets, each multiplexing module is arranged to contain a register group, and one or more sub-controllers are arranged between the main controller and the multiplexing module and used for further analyzing the data packets and controlling a target register group to complete read-write operation. In addition, the invention further provides a control method corresponding to the configuration device. Some embodiments of the present disclosure aim to solve the problems of high configuration switching time consumption and uncertain configuration switching time in the prior art by not increasing excessive complexity and area overhead.

Inventors

PAN YIHONG
QIN CHUJUN

Assignees

上海芯璐科技有限公司

Dates

Publication Date: 20260512
Application Date: 20260107

Claims (15)

1. A programmable logic device dynamic register configuration apparatus, comprising: an external controller for providing configuration instructions and configuration data; the main controller is used for receiving and analyzing the configuration data, generating a gating signal and reconstructing a data packet; at least one multiplexing module, each multiplexing module configured to contain a register set; one or more levels of sub-controllers are arranged between the main controller and the multiplexing module and used for further analyzing the data packet and controlling the target register group to complete read-write operation; and the read-back signal chain structure is used for merging read-back data of the multiplexing modules through logic operation and feeding back the merged read-back data to the main controller.
2. The arrangement according to claim 1, wherein, The main controller is connected with the external controller through an input validity mark line, an output validity mark line and a data line, wherein the input validity mark is used for indicating the validity of the configuration data, and the output validity mark is used for indicating the validity of the read-back data.
3. The arrangement according to claim 1, wherein, The main controller is connected with the sub-controllers, and the sub-controllers are connected with the subordinate sub-controllers or the multiplexing module through the gating lines and the data lines.
4. The arrangement according to claim 1, wherein, The logical operation is an or operation or an and operation.
5. The arrangement according to claim 1, wherein, The configuration device is configured to: When a primary sub-controller is arranged between the main controller and the multiplexing module, the main controller and the sub-controller, and the sub-controller and the multiplexing module are connected through a gate line and a data line; When a multi-stage sub-controller is arranged between the main controller and the multiplexing module, the multi-stage sub-controller comprises a first-stage sub-controller directly connected with the main controller and an N-stage sub-controller connected with an N-1-stage sub-controller, wherein N is a positive integer greater than 2, and the main controller and the first-stage sub-controller and the N-1-stage sub-controller are connected through a gating line and a data line.
6. A control method for the apparatus of any one of claims 1 to 5, comprising: the external controller generates an input validity flag and configuration data according to the read-write request; The main controller receives the configuration data, analyzes the hierarchical address and the register address of the target module, generates a gating signal and retransmits a data packet; the sub-controller receives the data packet, analyzes and generates gating, reading and writing, address and data signals of the register group; The register group executes read-write operation according to the control signal; and the read-back data output by the register group is merged through a chain structure and then returned to an external controller.
7. The method of claim 6, wherein the step of providing the first layer comprises, The configuration data includes: the first data packet comprises a hierarchical address, a register address and read-write control information of the target module; The second data packet, which is provided only at the time of the write operation, contains the configuration data to be written.
8. The method of claim 7, wherein the step of determining the position of the probe is performed, If the second data packet is not received after the write request but the read request is received, automatically ignoring the write request and executing the read request.
9. The method of claim 6, wherein the step of providing the first layer comprises, The read-back data is valid only when the output validity flag is high level, and the output validity flag is generated in synchronization with the valid read-back data.
10. The method of claim 6, wherein the read-back data is merged stage by stage through logic gates, and the ungated module outputs a logic 0.
11. A control method for the apparatus of any one of claims 1 to 5, comprising: generating a first input mark signal according to a system clock and a write instruction or generating a second input mark signal according to the system clock and a read instruction; Generating write configuration data or read configuration data according to the hierarchical information of the target multiplexing module; Transmitting the write configuration data and write data subsequent to the write configuration data when the first input flag signal is determined to be at a set level; the read configuration data is transmitted when the second input flag signal is determined to be at a set level.
12. The control method according to claim 11, characterized in that, When the first input flag signal is determined to be at a set level and the second input flag signal is determined to be at a set level after the first input flag signal is determined to be at a set level and the transmitted write data is determined to be null, the transmission of the write configuration data is abandoned and the read configuration data is transmitted.
13. The control method according to claim 11, characterized in that, The generating write configuration data or read configuration data according to the hierarchical information of the target multiplexing module includes: And generating the hierarchy information of each multiplexing module according to the relationship between each level of controllers and multiplexing modules in the chip device, and generating the hierarchy information of the target multiplexing module as the hierarchy information of the target multiplexing module.
14. The control method according to claim 11, characterized by further comprising: Generating an output flag signal after the second input flag signal according to a system clock; And when the output mark signal is determined to be at a set level, acquiring readback data.
15. A control method for the apparatus of any one of claims 1 to 5, comprising: generating a synchronous clock according to an external system clock; obtaining a first input flag signal or a second input flag signal; when the first input mark signal is determined to be at a set level, write configuration data and write data after the write configuration data are acquired, analyzing the write configuration data into a first-stage gating signal, gating a target controller or a target module of the first-stage gating signal according to the first-stage gating signal, and transmitting the rest of the write configuration data and the write data to the gated target controller or the gated target module; and analyzing the read configuration data to obtain a first-stage gating signal, gating a target controller or a target module of the first-stage gating signal according to the first-stage gating signal, and transmitting the rest read configuration data to the gated target controller or target module.

Description

Programmable logic device dynamic register configuration device and control method thereof Technical Field The disclosure relates to the technical field of chip design, in particular to a programmable logic device dynamic register configuration device and a control method thereof. Background Register configuration is a core concept in embedded systems and underlying hardware programming, which refers to the process of writing specific values to special function registers within a processor by software instructions, thereby controlling the behavior, state, and function of the hardware module. In the prior art, the most popular design is the unified memory map architecture. The processor core accesses all resources over a single system bus (e.g., AHB/AXI) and a lower speed peripheral bus (e.g., APB). The key point is that the Control and Status Registers (CSR) of the peripheral are assigned specific, fixed physical memory addresses by the designer. When the CPU (or DMA controller) executes standard store instructions (STR) to write data to these addresses, the hardware address decoder recognizes that the address falls within the address window of a particular peripheral and routes this write to the corresponding peripheral bus (e.g., APB). Eventually, the data is written to a physical register unit inside the target peripheral controller. The architecture is simple and visual, the software can configure the register by directly accessing the memory address through the pointer, but the address space allocation needs to be planned and fixed in advance. Furthermore, in bus standards like PCIe, there is a completely independent configuration address space. It is neither main memory space nor conventional I/O space. Accessing this configuration space has specialized protocols and transaction types (e.g., configuration Read/Write TLP for PCIe). The key mechanism is that when the system is started (or after hot plug), software (BIOS/OS) discovers the devices through an enumeration process, and allocates configuration space resources for the functions (functions) of each device. Registers within the device are mapped into their functionally corresponding configuration space header (e.g., PCI Configuration SPACE HEADER) and its extended capability structure. The software reads and writes the configuration registers by unique addresses consisting of Bus number (Bus), device number (Device), function number (Function), and register Offset (Offset). The above register configuration method requires that a separate and centralized register array space is allocated inside the chip, and this hardware layout is not suitable for use in a chip design with multiple multiplexing modules such as a programmable logic device. And if dynamic configuration of registers in a chiplet is required, too complex configuration logic, such as PCIe bus, is no longer suitable for such a scenario. Therefore, a simple dynamic register configuration mode that occupies little hardware resources and supports a reusable module is very necessary. Accordingly, there is a need for improvement and advancement in the art. It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present application and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the application section. Disclosure of Invention In order to solve at least one of the above problems, and one or more of other potential problems, the present disclosure proposes a configuration storage device of a reconfigurable array, which can solve the problems of high configuration switching time and uncertain configuration switching time in the prior art without increasing excessive complexity and area overhead, and a configuration storage system including the same. In a first aspect of the present disclosure, a programmable logic device dynamic register configuration apparatus is provided, which includes an external controller configured to provide configuration instructions and configuration data, a main controller configured to receive and parse the configuration data, generate strobe signals, and reconstruct data packets, at least one multiplexing module, each multiplexing module being configured to include a register group, and one or more sub-controllers disposed between the main controller and the multiplexing module, and configured to further parse the data packets and control a target register group to complete read/write operations. Further, in some embodiments, the main controller and the external controller are connected by an input validity flag line, an output validity flag line, and a data line. Further, in some embodiments, the main controller and the sub-controller, the sub-controller and the su