CN-121484637-B - Method for preparing semiconductor structure

CN121484637BCN 121484637 BCN121484637 BCN 121484637BCN-121484637-B

Abstract

The invention provides a preparation method of a semiconductor structure, which comprises the steps of forming a first sacrificial layer on one side of a layer to be etched, forming a mask layer on one side, away from the layer to be etched, of the first sacrificial layer, forming a first opening and a second opening in the mask layer, wherein the first opening penetrates through the mask layer, the thickness of the mask layer on one side, facing the layer to be etched, of the second opening is larger than zero, etching the first sacrificial layer at the bottom of the first opening, forming a third opening penetrating through the first sacrificial layer at the bottom of the first opening, etching the mask layer at the bottom of the second opening in the process of forming the third opening, and removing residual mask materials in an etching mode, etching the first sacrificial layer at the bottom of the second opening and the layer to be etched, forming a first pattern opening in the layer to be etched, and etching the mask layer at the bottom of the third opening in the process of forming the first pattern opening, and forming a second pattern opening in the layer to be etched.

Inventors

ZHAO WU
LUO CHEN
WANG JUN
LI LIUJING
LI SHUNFENG

Assignees

苏州长光华芯光电技术股份有限公司
苏州长光华芯半导体激光创新研究院有限公司

Dates

Publication Date: 20260512
Application Date: 20260112

Claims (7)

1. A method of fabricating a semiconductor structure, comprising: Forming a first sacrificial layer on one side of the layer to be etched; Forming a mask layer on one side of the first sacrificial layer, which is away from the layer to be etched; Forming a first opening and a second opening in the mask layer, wherein the first opening penetrates through the mask layer, and the thickness of the mask layer, facing to one side of the layer to be etched, of the second opening is larger than zero; Etching the first sacrificial layer at the bottom of the first opening, and forming a third opening penetrating through the first sacrificial layer at the bottom of the first opening; Etching the mask layer at the bottom of the second opening in the process of forming the third opening to enable the second opening to penetrate through the mask layer, wherein the bottom wall of the second opening is provided with residual mask materials; etching to remove the residual mask material; Etching the first sacrificial layer and the layer to be etched at the bottom of the second opening after the residual mask material is removed by etching, and forming a first pattern opening in the layer to be etched; and etching the layer to be etched at the bottom of the third opening in the process of forming the first pattern opening, and forming a second pattern opening in the layer to be etched, wherein the depth of the second pattern opening is larger than that of the first pattern opening.
2. The method for manufacturing a semiconductor structure according to claim 1, wherein the material of the first sacrificial layer is a semiconductor material, and the etching selectivity of the layer to be etched and the first sacrificial layer is 0.1-15 in the process of forming the first pattern opening and the second pattern opening.
3. The method of claim 1, further comprising forming a second sacrificial layer on one side of the layer to be etched, wherein the second sacrificial layer is made of a semiconductor material; forming the first sacrificial layer on one side of the layer to be etched comprises forming the first sacrificial layer on one side of the second sacrificial layer away from the layer to be etched, wherein the first sacrificial layer is a dielectric material; the process of forming the mask layer comprises forming the mask layer on one side of the second sacrificial layer away from the first sacrificial layer; forming a fourth opening in the first sacrificial layer in the process of etching the first sacrificial layer and the layer to be etched at the bottom of the second opening; etching the second sacrificial layer at the bottom of the third opening in the process of forming the fourth opening, and forming a fifth opening in the second sacrificial layer; And etching the second sacrificial layer at the bottom of the second opening in the process of etching the first sacrificial layer and the layer to be etched at the bottom of the second opening, and forming a sixth opening in the second sacrificial layer.
4. The method of fabricating a semiconductor structure of claim 3, wherein a bottom wall of the fourth opening has a residual dielectric material; The method for manufacturing the semiconductor structure further comprises the step of etching and removing the residual dielectric material before forming the sixth opening.
5. The method for manufacturing the semiconductor structure according to claim 1, wherein the layer to be etched is a photonic crystal layer, the number of the first openings is a plurality of the first openings, the plurality of the first openings are arranged periodically in the transverse direction, the number of the second openings is a plurality of the second openings, the plurality of the second openings are arranged periodically in the transverse direction, and the first openings and the second openings are arranged alternately.
6. The method of manufacturing a semiconductor structure according to claim 3, wherein an etching selectivity of the first sacrificial layer and the second sacrificial layer in forming the fourth opening and the fifth opening is greater than 5.
7. The method for manufacturing a semiconductor structure according to claim 1, wherein the layer to be etched is an imprint master, further comprising transferring the first pattern port and the second pattern port in the imprint master into a sub-plate having first protrusions corresponding to the first pattern port and second protrusions corresponding to the second pattern port therein; The preparation method of the semiconductor structure further comprises the steps of forming a photonic crystal layer on one side of an active layer, forming an imprinting adhesive layer on one side, away from the active layer, of the photonic crystal layer, imprinting the imprinting adhesive layer by utilizing the sub-plate, forming a first groove corresponding to the first protrusion and a second groove corresponding to the second protrusion in the imprinting adhesive layer, wherein the depth of the second groove is larger than that of the first groove, etching the photonic crystal layer by taking the imprinting adhesive layer as a mask, forming a third pattern opening in the photonic crystal layer at the bottom of the first groove, and forming a fourth pattern opening in the photonic crystal layer at the bottom of the second groove.

Description

Method for preparing semiconductor structure Technical Field The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor structure. Background The quantum cascade laser with the single transverse mode of the photonic crystal surface emitting semiconductor laser has important application in the aspects of industrial pumping, laser radar sensing, laser processing, gas sensing, quantum sensing and the like. The common photonic crystal surface emitting semiconductor laser is that a two-dimensional photonic crystal micro-nano structure is added into the surface emitting semiconductor laser, and single transverse mode output under the volume of a large active area is realized by utilizing the photonic band gap of the two-dimensional photonic crystal micro-nano structure in k space and the light field limitation in the plane direction, so that the high-brightness semiconductor laser with both the light beam quality and the high power is obtained. In the prior art, in order to realize single transverse mode output, a photonic band gap needs to be opened, and mode degeneracy is reduced, so that symmetry of a two-dimensional photonic crystal micro-nano structure needs to be broken, wherein the method comprises the steps of realizing a double-lattice photonic crystal or a multi-lattice photonic crystal by adopting an asymmetric pattern on an x-y plane, and etching patterns of different unit cell elements in the multi-lattice photonic crystal to different depths in a z direction (epitaxial growth direction). However, the quality of the pattern and the process cost cannot be considered, so that the two-dimensional photonic crystal micro-nano structure cannot realize mass production. Disclosure of Invention Therefore, the technical problem to be solved by the invention is how to overcome the defect that the quality of the pattern and the process cost cannot be considered in the prior art, so as to provide a preparation method of the semiconductor structure. The application provides a preparation method of a semiconductor structure, which comprises the steps of forming a first sacrificial layer on one side of a layer to be etched, forming a mask layer on one side of the first sacrificial layer, which is away from the layer to be etched, forming a first opening and a second opening in the mask layer, wherein the first opening penetrates through the mask layer, the thickness of the mask layer on one side of the second opening, which faces the layer to be etched, is larger than zero, etching the first sacrificial layer at the bottom of the first opening, forming a third opening penetrating through the first sacrificial layer at the bottom of the first opening, etching the mask layer at the bottom of the second opening in the process of forming the third opening, enabling the second opening to penetrate through the mask layer, and the bottom wall of the second opening is provided with a residual mask material, etching the first sacrificial layer and the layer at the bottom of the second opening after the residual mask material is removed, forming a first pattern in the layer to be etched, forming a third pattern at the bottom of the first pattern, and forming the second pattern at the bottom of the first pattern, wherein the depth of the first pattern is larger than the first pattern in the process of forming the third pattern. Optionally, the first sacrificial layer is made of a semiconductor material, and in the process of forming the first pattern opening and the second pattern opening, the etching selection ratio of the layer to be etched to the first sacrificial layer is 0.1-15. Optionally, the method further comprises the steps of forming a second sacrificial layer on one side of the to-be-etched layer, wherein the material of the second sacrificial layer is a semiconductor material, forming the first sacrificial layer on one side of the to-be-etched layer comprises the step of forming the first sacrificial layer on one side of the second sacrificial layer, which faces away from the to-be-etched layer, and the first sacrificial layer is a dielectric material, forming the mask layer on one side of the second sacrificial layer, which faces away from the first sacrificial layer, forming a fourth opening in the first sacrificial layer, and forming a fifth opening in the second sacrificial layer, wherein the second sacrificial layer on the bottom of the second opening is etched, and the sixth opening is formed in the second sacrificial layer. Optionally, the bottom wall of the fourth opening is provided with a residual dielectric material, and the preparation method of the semiconductor structure further comprises the step of etching to remove the residual dielectric material before forming the sixth opening. Optionally, the layer to be etched is a photonic crystal layer, the number of the first openings is a plurality of the first openings, the first openings are