CN-121485612-B - High-linearity low-noise amplifier and radio frequency chip

CN121485612BCN 121485612 BCN121485612 BCN 121485612BCN-121485612-B

Abstract

The invention relates to the technical field of wireless communication, and provides a high-linearity low-noise amplifier and a radio frequency chip, which comprise an input matching module, a power amplification module and an output matching module which are electrically connected in sequence, wherein a grid electrode of a first MOS tube of the power amplification module is connected with a first end of a first capacitor, a source electrode of the first MOS tube is respectively connected with a second end of the first capacitor, a first end of a first inductor and a first end of a second inductor, a second end of the first inductor is grounded, the first inductor is coupled with the second inductor, a second end of the second inductor is respectively connected with the first end of the second capacitor and a source electrode of the second MOS tube, a grid electrode of the second MOS tube is respectively connected with a second end of the second capacitor and a grid electrode of the first MOS tube, and a drain electrode of the second MOS tube is connected with a drain electrode of the first MOS tube and a source electrode of a third MOS tube. The high-linearity low-noise amplifier has adjustable gain, low noise, high linearity and low power consumption.

Inventors

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Assignees

深圳飞骧科技股份有限公司

Dates

Publication Date: 20260508
Application Date: 20260107

Claims (10)

1. The high-linearity low-noise amplifier comprises an input matching module, a power amplification module and an output matching module which are electrically connected in sequence, wherein the input matching module is used for accessing radio frequency signals and realizing input impedance matching, the power amplification module is used for amplifying the radio frequency signals, and the output matching module is used for outputting the amplified radio frequency signals after output impedance matching; The grid electrode of the first MOS tube is used as an input end of the power amplification module, the source electrode of the first MOS tube is respectively connected with the first end of the first inductor and the first end of the second inductor, the drain electrode of the first MOS tube is connected to the source electrode of the third MOS tube, the first end of the first capacitor is connected with the grid electrode of the first MOS tube, the second end of the first capacitor is connected with the source electrode of the first MOS tube, the second end of the first inductor is grounded, the first inductor and the second inductor are mutually coupled, the second end of the second inductor is respectively connected with the first end of the second capacitor and the source electrode of the second MOS tube, the grid electrode of the second MOS tube is respectively connected with the second end of the second capacitor and the grid electrode of the first MOS tube, the drain electrode of the second MOS tube is respectively connected with the drain electrode of the first MOS tube and the source electrode of the third MOS tube, the drain electrode of the third MOS tube is used as an output end of the first MOS tube, the second inductor is grounded, the first MOS tube is connected with the second MOS tube, the second MOS tube is used for providing a feedback offset circuit, and the second MOS tube is used for realizing the offset of the output state of the second MOS tube, and the second MOS tube is used for realizing the offset.
2. The high linearity low noise amplifier of claim 1, wherein the high linearity low noise amplifier comprises a first resistor, a first end of the first resistor is used for connecting a first external logic control circuit, a second end of the first resistor is connected with a gate of the first MOS transistor, and the first external logic control circuit is used for providing a first gate bias voltage for the first MOS transistor.
3. The high linearity low noise amplifier of claim 2 further comprising a second resistor, a first end of the second resistor being connected to a second external logic control circuit, a second end of the second resistor being connected to a gate of the second MOS transistor, the second external logic control circuit being configured to provide a second gate bias voltage to the second MOS transistor.
4. A high linearity low noise amplifier according to claim 3, wherein the first gate bias voltage is different from the second gate bias voltage.
5. The high linearity low noise amplifier of claim 1 further comprising a third resistor, a first end of the third resistor being connected to a gate of the third MOS transistor, a second end of the third resistor being connected to the external logic control circuit.
6. The high linearity low noise amplifier of claim 1, wherein said output matching module comprises a third inductor, a fourth inductor, a switch, a third capacitor, a fourth capacitor, a fifth capacitor, and a fourth resistor of adjustable resistance; The first end of the third inductor is used as an input end of the output matching module, the first end of the third inductor is respectively connected with an output end of the power amplification module, a control end of the switch and a first end of the fourth resistor, the second end of the third inductor is respectively connected with the first end of the fourth inductor and the first end of the fifth capacitor, the output end of the switch is respectively connected with the first end of the third capacitor and the first end of the fourth capacitor, the second end of the fourth capacitor is respectively connected with the second end of the fourth resistor and the second end of the fourth inductor and is used for being connected with a power supply, and the second end of the third capacitor is connected with the second end of the fifth capacitor and is used as an output end of the output matching module.
7. The high linearity low noise amplifier of claim 1, wherein said input matching block comprises a fifth inductor and a sixth capacitor, a first end of said fifth inductor being an input of said input matching block, a second end of said fifth inductor being connected to a first end of said sixth capacitor, a second end of said sixth capacitor being an output of said input matching block.
8. The high linearity, low noise amplifier of claim 6, further comprising a seventh capacitor, a first end of the seventh capacitor connected to the power supply, a second end of the seventh capacitor connected to ground.
9. The high linearity low noise amplifier of claim 1, wherein said first capacitance and said second capacitance are tuning capacitances.
10. A radio frequency chip comprising the high linearity low noise amplifier of any of claims 1-9.

Description

High-linearity low-noise amplifier and radio frequency chip Technical Field The invention relates to the technical field of wireless communication, in particular to a high-linearity low-noise amplifier and a radio frequency chip. Background As a first stage active device of the radio frequency front end system, a high linearity Low Noise Amplifier (LNA) generally needs a certain gain to amplify weak signals received from an antenna and has a certain noise suppression capability for a subsequent stage module, and also needs very low noise itself to ensure the receiving sensitivity of the system. Meanwhile, higher linearity is required to ensure that an RX (receiving) branch of the receiver can work normally when a larger high interference signal appears in a link, so that the balance of gain, noise figure and linearity is a problem to be considered in design. In the related art, the high-linearity low-noise amplifier comprises an input matching module, an amplifying module and an output matching module, wherein the input matching module is connected with an input signal of the low-noise amplifier, the amplifying module is used for amplifying the signal, the output matching module is connected with an output end of the low-noise amplifier, and the output matching module is used for inhibiting an interference signal and outputting the processed signal to the output end of the low-noise amplifier. However, in the current rf front-end link, the low noise amplifier itself needs to perform adjustment of the gain shift to meet the receiving gain under different conditions, and is limited by gain switching and power consumption, so that it is difficult to obtain a good balance between the noise coefficient and linearity of the LNA itself under all shift positions, and the current mainstream design is to implement linearity enhancement by performing input attenuation or source negative feedback, which has a large influence on noise, so that it is a problem that needs to be solved at present to enhance linearity with a small noise coefficient and power consumption. Disclosure of Invention Aiming at the defects of the prior art, the invention provides a high-linearity low-noise amplifier to solve the problem of low linearity of the existing high-linearity low-noise amplifier. In order to solve the technical problems, the invention adopts the following technical scheme: the embodiment of the invention provides a high-linearity low-noise amplifier, which comprises an input matching module, a power amplification module and an output matching module which are electrically connected in sequence, wherein the input matching module is used for accessing a radio frequency signal and realizing input impedance matching, the power amplification module is used for amplifying the radio frequency signal, and the output matching module is used for carrying out output impedance matching and outputting on the amplified radio frequency signal; The grid electrode of the first MOS tube is used as an input end of the power amplification module, the source electrode of the first MOS tube is respectively connected with the first end of the first inductor and the first end of the second inductor, the drain electrode of the first MOS tube is connected to the source electrode of the third MOS tube, the first end of the first capacitor is connected with the grid electrode of the first MOS tube, the second end of the first capacitor is connected with the source electrode of the first MOS tube, the second end of the first inductor is grounded, the first inductor and the second inductor are mutually coupled, the second end of the second inductor is respectively connected with the first end of the second capacitor and the source electrode of the second MOS tube, the grid electrode of the second MOS tube is respectively connected with the second end of the second capacitor and the grid electrode of the first MOS tube, the drain electrode of the second MOS tube is respectively connected with the drain electrode of the first MOS tube and the source electrode of the third MOS tube, the drain electrode of the third MOS tube is used as an output end of the first MOS tube, the second inductor is grounded, the first MOS tube is connected with the second MOS tube, the second MOS tube is used for providing a feedback offset circuit, the second MOS tube is used for realizing the offset of the output state of the second MOS tube, and the second MOS tube is used for realizing the offset output voltage. Preferably, the high linearity low noise amplifier includes a first resistor, a first end of the first resistor is used for being connected with a first external logic control circuit, a second end of the first resistor is connected with a gate of the first MOS tube, and the first external logic control circuit is used for providing a first gate bias voltage for the first MOS tube. Preferably, the high linearity low noise amplifier further comprises a second resist