CN-121485641-B - Chip single-wire IIC signal analysis method based on functional test

CN121485641BCN 121485641 BCN121485641 BCN 121485641BCN-121485641-B

Abstract

The invention relates to the technical field of signal analysis, and particularly discloses a chip single-wire IIC signal analysis method based on functional test, comprising the following steps of S1, carrying out dynamic window median filtering on an input signal, and effectively eliminating signal jitter and burrs through dynamic expansion and median replacement of a sliding window to output a smooth digital signal; the method comprises the steps of S2, generating a virtual clock, obtaining a time interval sequence based on jump edge detection, calculating interval variance by adopting a sliding window, screening effective intervals according to a variance threshold value, and finally equally dividing to generate the virtual clock, S3, sampling the clock in the center of a signal steady-state interval, analyzing sampled data according to an IIC protocol state machine, and finishing data decoding, wherein the whole process is realized by a pure software algorithm, hardware limitation is broken through, and analysis precision and equipment compatibility are obviously improved.

Inventors

CHEN DACHUAN
ZHANG YUE
YANG AIMIN
ZHANG MENGJIE
QI YUNFENG
LI YUXIN

Assignees

悦芯科技股份有限公司

Dates

Publication Date: 20260508
Application Date: 20251107

Claims (8)

1. The method for analyzing the single-wire IIC signal of the chip based on the functional test is characterized by comprising the following steps of: step S1, adopting a dynamic expansion window median filtering algorithm to filter an input single-line IIC signal so as to eliminate jitter and burrs in the signal and output a smoothed digital signal; Step S2, detecting jump edges of the smoothed digital signal to obtain a time stamp sequence and obtain time intervals between continuous jump edges, adopting a sliding window to obtain variance of the time intervals, and screening the time intervals based on the variance and a preset variance threshold to filter noise intervals and obtain effective time intervals; And S3, utilizing the virtual clock signal to perform center sampling in a steady-state interval of the IIC signal to obtain sampling data, analyzing the sampling data according to an IIC protocol state machine, and outputting decoded IIC data.
2. The method for analyzing the single-chip IIC signal based on the functional test according to claim 1, wherein in step S1, the process of the dynamic extended window median filtering algorithm includes: Initializing a dynamic expansion window, if the number of data points in the dynamic expansion window is insufficient for median calculation, dynamically expanding the boundary of the dynamic expansion window, wherein the left boundary of the dynamic expansion window is preferentially expanded leftwards, and if the left boundary of the dynamic expansion window cannot be expanded, the right boundary of the dynamic expansion window is expanded rightwards.
3. The method for analyzing a single-wire IIC signal on a chip according to claim 2, wherein in step S1, during the initialization of the dynamic expansion window, the size of the dynamic expansion window defaults to 3, and the size of the dynamic expansion window is dynamically adjusted based on signal quality.
4. The method for analyzing a single-chip IIC signal based on a functional test according to claim 1, wherein in step S2, the setting process of the variance threshold includes: And obtaining an average value T of each time interval in the current sliding window, and setting the variance threshold value to be alpha T, wherein alpha is a preset configurable parameter, and alpha=0.2.
5. The method for analyzing a single-wire IIC signal on a chip based on a functional test as claimed in claim 4, wherein in step S2, the process of screening the time interval includes: And for any time interval in the sliding window, if the time interval is larger than the sum of the average value and the variance threshold or smaller than the difference between the average value and the variance threshold, judging the time interval as noise, and filtering.
6. The method for analyzing a single-chip IIC signal based on a functional test of claim 1, wherein in step S2, the generating process of the virtual clock signal includes equally dividing the effective time interval after noise filtering to obtain a virtual clock signal with a constant period.
7. The method for analyzing the single-chip IIC signal based on the functional test of claim 1, wherein in step S3, the process of performing the center sampling in the steady-state interval includes: And sampling the smoothed digital signal in the central position of the clock period in one clock period of the virtual clock signal.
8. The method for analyzing the single-wire IIC signal based on the functional test of claim 1, wherein in step S3, the process of analyzing the sampled data according to the IIC protocol state machine includes identifying and converting the start condition, the data bit, the response bit, and the stop condition.

Description

Chip single-wire IIC signal analysis method based on functional test Technical Field The invention relates to the technical field of signal analysis, in particular to a chip single-wire IIC signal analysis method based on functional test. Background In the field of automated testing of integrated circuits, automated Test Equipment (ATE) is widely used to perform functional and performance verification on chips (DUTs). In many chip communication protocols, IIC (Inter-INTEGRATED CIRCUIT) buses are commonly used because of their simple structure and small pins. The conventional IIC bus uses separate serial data line (SDA) and Serial Clock Line (SCL) for synchronous communication. However, to further conserve pin resources, a single-wire IIC protocol was derived that combines data and clock signals for transmission over a single line, no longer providing an independent clock signal. This feature poses a significant challenge to the signal capture mechanisms of existing ATE tools. Conventional ATE relies heavily on a stable, independent clock signal as a sampling reference when capturing DUT signals. For single-wire IIC signals, the lack of this reference results in the ATE not being able to directly and reliably synchronize and parse the data signal. While some high-end ATE stations provide hardware-based pattern Matching (MATCH) functionality to attempt to capture such signals, this approach is limited by its fixed hardware circuit architecture, which suffers from inherent drawbacks of poor flexibility, complex configuration, and inability to accommodate all types of DUTs, resulting in poor test coverage and inefficiency. Therefore, there is an urgent need in the prior art to find a signal analysis method that does not depend on an independent clock signal, can overcome jitter interference of a single-wire IIC signal, and has wide applicability, so as to realize efficient and accurate testing of a single-wire IIC protocol chip. Disclosure of Invention The invention aims to provide a chip single-wire IIC signal analysis method based on functional test, which solves the following technical problems. The aim of the invention can be achieved by the following technical scheme: the method for analyzing the single-wire IIC signal of the chip based on the functional test comprises the following steps: step S1, adopting a dynamic expansion window median filtering algorithm to filter an input single-line IIC signal so as to eliminate jitter and burrs in the signal and output a smoothed digital signal; Step S2, detecting jump edges of the smoothed digital signal to obtain a time stamp sequence and obtain time intervals between continuous jump edges, adopting a sliding window to obtain variance of the time intervals, and screening the time intervals based on the variance and a preset variance threshold to filter noise intervals and obtain effective time intervals; And S3, utilizing the virtual clock signal to perform center sampling in a steady-state interval of the IIC signal to obtain sampling data, analyzing the sampling data according to an IIC protocol state machine, and outputting decoded IIC data. As a further scheme of the invention, the process of the dynamic expansion window median filtering algorithm comprises the following steps: Initializing a dynamic expansion window, if the number of data points in the dynamic expansion window is insufficient for median calculation, dynamically expanding the boundary of the dynamic expansion window, wherein the left boundary of the dynamic expansion window is preferentially expanded leftwards, and if the left boundary of the dynamic expansion window cannot be expanded, the right boundary of the dynamic expansion window is expanded rightwards. In the initialization process of the dynamic expansion window, the size of the dynamic expansion window defaults to 3, and the size of the dynamic expansion window is dynamically adjusted based on signal quality. The setting process of the variance threshold value comprises the following steps: And obtaining an average value T of each time interval in the current sliding window, and setting the variance threshold value to be alpha T, wherein alpha is a preset configurable parameter, and alpha=0.2. As a further proposal of the invention, the process of screening the time interval comprises the following steps: And for any time interval in the sliding window, if the time interval is larger than the sum of the average value and the variance threshold or smaller than the difference between the average value and the variance threshold, judging the time interval as noise, and filtering. The generation process of the virtual clock signal comprises the steps of equally dividing the effective time interval after noise is filtered, and obtaining the virtual clock signal with a constant period. As a further proposal of the invention, the process of center sampling in the steady-state interval comprises: And sampling the smoothed digital signal in