Search

CN-121485651-B - Dynamic comparator and integrated circuit chip based on pulse width modulation

CN121485651BCN 121485651 BCN121485651 BCN 121485651BCN-121485651-B

Abstract

The invention discloses a dynamic comparator and an integrated circuit chip based on pulse width modulation, and belongs to the technical field of integrated circuits. According to the invention, the clock modulation module based on pulse width modulation is introduced into the clock path of the dynamic comparator, so that two paths of reset clock signals are independently regulated and controlled. The module comprises two adjustable delay chains and a logic OR gate, the low level pulse width difference of two paths of clocks is finely adjusted through a digital control signal, and a controllable initial voltage difference is generated between key nodes in the comparator in a resetting stage of the comparator, so that the inherent offset voltage is accurately counteracted. The calibration process works only in the reset phase and is completely isolated from the signal path in the comparison phase, avoiding the introduction of additional parasitic parameters. The invention has the advantages of high-precision calibration and high-speed performance, compact structure, low power consumption and easy digital integration.

Inventors

  • Request for anonymity
  • Request for anonymity
  • Request for anonymity
  • Request for anonymity
  • Request for anonymity

Assignees

  • 成都星拓微电子科技股份有限公司

Dates

Publication Date
20260512
Application Date
20260109

Claims (8)

  1. 1. A pulse width modulation based dynamic comparator comprising: a dynamic comparator body configured to switch between a reset phase and a compare phase based on a clock signal; the clock modulation module is configured to perform pulse width modulation on the global clock signal, so that the modulated first clock signal and the modulated second clock signal have independent low-level pulse widths; the first clock signal and the second clock signal respectively control a control reset tube of a first node and a control reset tube of a second node in the dynamic comparator; the clock modulation module includes: a first adjustable delay chain for generating a first controllable delay for the global clock signal; A first logic or gate having a first input receiving the global clock signal, a second input receiving an output signal of the first adjustable delay chain, and an output generating the first clock signal; A second adjustable delay chain for generating a second controllable delay for the global clock signal; a second logic or gate, a first input end of which receives the global clock signal, a second input end of which receives the output signal of the second adjustable delay chain, and an output end of which generates the second clock signal; The dynamic comparator body includes: A differential input pair of transistors having gates for receiving a differential input signal; The positive feedback latch is connected between a first node and a second node in the dynamic comparator and is used for amplifying and locking the voltage difference between the first node and the second node in the dynamic comparator; a tail current tube, the grid of which receives the global clock signal and is used for providing working current for the dynamic comparator in a comparison stage; The reset tube comprises the control reset tube, the control reset tube of the first node is conducted under the control of the first clock signal to reset the first node in the dynamic comparator, and the control reset tube of the second node is conducted under the control of the second clock signal to reset the second node in the dynamic comparator.
  2. 2. The pulse width modulation based dynamic comparator of claim 1, wherein: the clock modulation module controls the first node and the second node in the dynamic comparator to generate initial voltage difference at different charging time of the reset stage.
  3. 3. The pulse width modulation based dynamic comparator of claim 1, wherein: And the offset voltage calibration value of the dynamic comparator and the delay amount of the first adjustable delay chain or the second adjustable delay chain are in linear proportional relation.
  4. 4. A dynamic pulse width modulation based comparator according to claim 3, wherein: the delay amount of the first adjustable delay chain and the delay amount of the second adjustable delay chain can be adjusted independently by a digital signal.
  5. 5. The pulse width modulation based dynamic comparator of claim 1, wherein: When the first adjustable delay chain is set to a non-zero delay and the second adjustable delay chain is set to a zero delay, a negative initial voltage difference is generated between a first node and a second node inside the dynamic comparator for compensating a positive offset voltage.
  6. 6. The pulse width modulation based dynamic comparator of claim 1, wherein: When the second adjustable delay chain is set to a non-zero delay and the first adjustable delay chain is set to a zero delay, a positive initial voltage difference is generated between a first node and a second node inside the dynamic comparator for compensating a negative offset voltage.
  7. 7. Pulse width modulation based dynamic comparator according to any of the claims 1 to 5, characterized in that: In the comparison phase, the clock modulation module is in an electrical isolation state with the decision path of the dynamic comparator.
  8. 8. An integrated circuit chip, characterized in that: integrated with a pulse width modulation based dynamic comparator as claimed in any one of claims 1 to 7.

Description

Dynamic comparator and integrated circuit chip based on pulse width modulation Technical Field The invention relates to the technical field of integrated circuits, in particular to a dynamic comparator based on pulse width modulation and an integrated circuit chip. Background In the field of high-speed digital circuits and memory interfaces, particularly double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM) interfaces, the data decision speed and accuracy of the receiving end directly determine the upper limit of the performance of the whole system. As data transmission rates enter fifth generation (DDR 5) and higher standards, signals experience severe high frequency loss when transmitted through packaging and printed circuit board channels, resulting in signal amplitude attenuation and increased intersymbol interference. To compensate for channel insertion loss, modern receivers commonly employ decision feedback equalizers (Decision Feedback Equalizer, DFE) to cancel the post-cursor interference of the data. One of the core components of the DFE is a dynamic comparator that is required to make accurate decisions on high-speed signals of small amplitude. The dynamic comparator is used as a key signal decision unit, and the ideal characteristic of the dynamic comparator is that the dynamic comparator turns over when the input differential voltage is zero. However, in the actual manufacturing process, due to factors such as process deviation and size mismatch of the transistor, a non-negligible input offset voltage is introduced. The offset voltage can cause the deviation of the actual decision threshold of the dynamic comparator to cause erroneous decision, thereby remarkably improving the error rate of the system and becoming one of main bottlenecks for restricting the performance of a receiving end. Therefore, the accurate offset voltage calibration of the dynamic comparator is an indispensable ring in the design of the high-speed high-reliability interface chip. FIG. 1 is a circuit diagram of a dynamic comparator employing an adjustable input pair tube array. Fig. 2 is a circuit diagram of a dynamic comparator employing an array of adjustable capacitors. The typical schemes in the prior art are two of the two. As shown in fig. 1, the first approach is based on an adjustable input to a calibration technique for the tube array. Based on the differential input pair of the dynamic comparator, the technology connects in parallel a plurality of small input pair tubes (such as M2 and M3) which are controlled by digital signals and have sizes weighted according to binary. By controlling the number of these additional pairs of transistors open, the equivalent transconductance of the input pair is fine tuned to compensate for the offset. However, to achieve high accuracy calibration, a large number of micro-transistors need to be integrated, which can significantly increase the input capacitance and chip area of the dynamic comparator. The increased parasitic capacitance reduces the response speed of the dynamic comparator, contrary to the need for high-speed applications. As shown in fig. 2, the second approach is based on a calibration technique of the tunable capacitor array. The scheme connects a capacitor array controlled by a switch in parallel with a key node (such as the drain electrode of an input pair tube) inside the dynamic comparator. During the reset phase of the dynamic comparator, the node voltage is changed by injecting charge into the nodes and adjusting the accessed capacitance value to counteract the offset. While this approach works well, the capacitive array itself introduces large parasitic parameters and area overhead. More importantly, the capacitance value in the integrated circuit is susceptible to fluctuations in process angle, operating voltage and ambient temperature, resulting in unstable calibration amounts, reducing the reliability and robustness of calibration. In summary, while the existing offset calibration technology pursues high precision, it is often unavoidable to introduce additional parasitic effects, area costs or stability issues, limiting its application in very high speed scenarios. Therefore, there is a great need in the art for a new solution that can achieve high accuracy, high stability misalignment calibration without sacrificing the dynamic comparator core speed. Disclosure of Invention In order to alleviate or partially alleviate the above technical problem, the solution of the present invention is as follows: In one aspect, the invention discloses a dynamic comparator based on pulse width modulation, comprising: a dynamic comparator body configured to switch between a reset phase and a compare phase based on a clock signal; the clock modulation module is configured to perform pulse width modulation on the global clock signal, so that the modulated first clock signal and the modulated se