CN-121486568-B - Video encoding and decoding display method, device, electronic equipment and computer readable medium

CN121486568BCN 121486568 BCN121486568 BCN 121486568BCN-121486568-B

Abstract

Embodiments of the present disclosure disclose a video codec display method, apparatus, electronic device, and computer readable medium. The method comprises the steps of splitting each video frame to be encoded to obtain a video frame block set to be encoded, determining a video frame block encoding channel set meeting an interrupt trigger condition, carrying out key video frame block peak shifting processing on each video frame block to be encoded to obtain a key video frame encoding block set and a channel delay encoding time difference set, carrying out video encoding on each video frame block to be encoded to obtain a video frame block channel code stream set, determining decoding splicing threads of the video frame block channel code stream set to obtain a decoding splicing thread set, carrying out video frame block decoding splicing on the video frame block channel code stream set to obtain a decoded video, and carrying out video frame display processing on the decoded video. The implementation mode can improve the balance of the code stream after video coding, improve the stability and instantaneity of video transmission and reduce the delay of video transmission.

Inventors

ZHOU XUEWU
DONG YU
ZHANG YUNDONG
Zhan Shenping
DENG ZHENG
ZHANG CHENG
SHI CHANGMING

Assignees

北京中星微人工智能芯片技术有限公司
福建警察学院
中星微技术股份有限公司

Dates

Publication Date: 20260505
Application Date: 20251106

Claims (7)

1. A video codec display method, comprising: Responding to the determination that an image splitting coding transmitting end receives video to be coded, splitting each video frame to be coded included in the video to be coded according to coding equipment information of the image splitting coding transmitting end so as to generate a video frame block group to be coded, and obtaining a video frame block group set to be coded; In response to detecting that the set of video frame blocks to be encoded meets an interrupt trigger condition, determining a set of video frame block encoding channels meeting the interrupt trigger condition; performing key video frame block peak shifting processing on each video frame block to be encoded included in the video frame block encoding channel set to obtain a key video frame encoding block set and a channel delay encoding time difference set; Controlling the video frame block coding channel set to carry out video coding on each corresponding video frame block to be coded according to the key video frame coding block set and the channel delay coding time difference set to obtain a video frame block channel code stream set; in response to determining that the decoding merging receiving end receives the video frame block channel code stream set, determining a decoding splicing thread of each video frame block channel code stream in the video frame block channel code stream set, and obtaining a decoding splicing thread set; According to the decoding and splicing thread set, video frame block decoding and splicing processing is carried out on the video frame block channel code stream set, so as to obtain a decoded video; And in response to determining that the video display receives the decoded video, performing video frame display processing on the decoded video.
2. The method of claim 1, wherein the determining, in response to detecting that the set of video frame blocks to be encoded satisfies an interrupt trigger condition, a set of video frame block encoding channels that satisfies an interrupt trigger condition comprises: Creating a video frame block buffer area set and a buffer filling state monitor set, wherein the video frame block buffer area set and the buffer filling state monitor set have a one-to-one correspondence; In response to determining that at least one buffer filling state monitor representing completion of filling of the video frame block buffer exists in the buffer filling state monitor set, determining at least one video frame block set to be encoded stored in at least one video frame block buffer corresponding to the at least one buffer filling state monitor as a target video frame block set to be encoded; Generating a video frame block filling interrupt signal set in response to determining that the target set of video frame blocks to be encoded meets an interrupt trigger condition; and according to the video frame block filling interrupt signal set, determining a video frame block coding channel set meeting an interrupt trigger condition.
3. The method of claim 1, wherein performing key video frame block peak shifting processing on each video frame block to be encoded included in the video frame block encoding channel set to obtain a key video frame encoding block set and a channel delay encoding time difference set, includes: performing filling completion time sequence sequencing on the video frame block coding channel set to obtain a video frame block coding channel sequence; determining the position information of key video frame blocks of each video frame block to be coded included in each video frame block coding channel in the video frame block coding channel sequence according to the peak staggering condition of the key video frame blocks of the preset channel, and obtaining a key video frame block position information set; and determining a channel delay coding time difference set and a key video frame coding block set of the video frame block coding channel sequence according to the channel key video frame block position information set.
4. The method of claim 1, wherein the performing video frame block decoding and splicing processing on the video frame block channel code stream set according to the decoding and splicing thread set to obtain a decoded video comprises: Controlling the decoding splicing thread set, and decoding the video frame block channel code stream set to obtain a decoded video frame block group set; performing zero clearing treatment on the display buffer zone of the video display end to obtain a zero cleared display buffer zone; Storing a non-overlapping decoded video frame block set included in the decoded video frame block set to the clear display buffer region through direct memory access; For each overlapping decoded video frame block region in the set of overlapping decoded video frame block regions comprised by the set of decoded video frame block groups, performing the following pixel blending step: Performing incremental transparency transformation on the overlapping region of the first decoding video frame block corresponding to the overlapping decoding video frame block region to obtain a first overlapping region transparency set; performing decreasing transparency transformation on the overlapping area of the second decoding video frame block corresponding to the overlapping decoding video frame block area to obtain a second overlapping area transparency set; according to the first overlapping region transparency set and the second overlapping region transparency set, carrying out pixel mixing on the overlapping region of the first decoding video frame block and the overlapping region of the second decoding video frame block to obtain a decoding overlapping video frame block region; Transmitting each obtained decoded overlapped video frame block area to the clear display buffer area through direct memory access; And splicing the decoded overlapping video frame block area sets and the non-overlapping decoded video frame block sets which are stored in the clear display buffer area to obtain the decoded video.
5. A video codec display device comprising: The splitting unit is configured to respond to the determination that the image splitting coding transmitting end receives the video to be coded, and split each video frame to be coded included in the video to be coded according to the coding equipment information of the image splitting coding transmitting end so as to generate a video frame block group to be coded and obtain a video frame block group set to be coded; a first determining unit configured to determine a set of video frame block encoding channels satisfying an interrupt trigger condition in response to detecting that the set of video frame block groups to be encoded satisfies the interrupt trigger condition; The key video frame block peak shifting unit is configured to perform key video frame block peak shifting processing on each video frame block to be encoded included in the video frame block encoding channel set to obtain a key video frame encoding block set and a channel delay encoding time difference set; the control unit is configured to control the video frame block coding channel set to carry out video coding on each corresponding video frame block to be coded according to the key video frame coding block set and the channel delay coding time difference set, so as to obtain a video frame block channel code stream set; a second determining unit configured to determine a decoding splicing thread of each video frame block channel code stream in the video frame block channel code stream set in response to determining that the decoding merging receiving end receives the video frame block channel code stream set, and obtain a decoding splicing thread set; the video frame block decoding and splicing unit is configured to perform video frame block decoding and splicing processing on the video frame block channel code stream set according to the decoding and splicing thread set to obtain a decoded video; and a video frame display unit configured to perform video frame display processing on the decoded video in response to determining that the video display unit receives the decoded video.
6. An electronic device, comprising: One or more processors; a storage device having one or more programs stored thereon, When executed by the one or more processors, causes the one or more processors to implement the method of any of claims 1-4.
7. A computer readable medium having stored thereon a computer program, wherein the computer program, when executed by a processor, implements the method of any of claims 1-4.

Description

Video encoding and decoding display method, device, electronic equipment and computer readable medium Technical Field Embodiments of the present disclosure relate to the field of computer technology, and in particular, to a video codec display method, apparatus, electronic device, and computer readable medium. Background With the growing demand for high definition video, especially in remote real-time application scenarios (e.g. online conferencing, telemedicine), higher demands are being placed on high stability and low latency of video codecs. For encoding and decoding display of video, a method is generally adopted, wherein video frames are encoded for the video to be encoded, and a video frame code stream is obtained. And then, video frame decoding is carried out on the video frame code stream, a decoded video is obtained, and terminal display is carried out on the decoded video. However, in practice, it is found that when the above manner is adopted to perform encoding and decoding display on video, there are often technical problems that the whole frame of the video frame is encoded, adjustment on the key video frame and the common frame is lacking, under the condition that bandwidth fluctuation exists in the video transmission process, the stability of the video code stream is low, meanwhile, in the decoding process, decoding needs to be performed after the key video frame is decoded, the decoding delay is large, the video output delay is high, and the video frame transmission and display duration is prolonged. The above information disclosed in this background section is only for enhancement of understanding of the background of the disclosed concept and, therefore, it may contain information that does not form the prior art that is known to those of ordinary skill in the art in this country. Disclosure of Invention The disclosure is in part intended to introduce concepts in a simplified form that are further described below in the detailed description. The disclosure is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Some embodiments of the present disclosure propose video codec display methods, apparatuses, electronic devices, and computer-readable media to solve one or more of the technical problems mentioned in the background section above. In a first aspect, some embodiments of the present disclosure provide a video encoding and decoding display method, which includes receiving a video to be encoded in response to determining that an image splitting encoding transmitting end receives the video to be encoded, splitting each video frame included in the video to be encoded according to encoding device information of the image splitting encoding transmitting end to generate a video frame block set to be encoded, determining a video frame block encoding channel set satisfying an interrupt trigger condition in response to detecting that the video frame block set to be encoded satisfies the interrupt trigger condition, performing a key video frame block staggering process on each video frame block included in the video frame block encoding channel set to obtain a key video frame encoding block set and a channel delay encoding time difference set, performing video encoding on each corresponding video frame to be encoded according to the key video frame encoding block set and the channel delay encoding time difference set to obtain a video frame block channel code set, receiving a video frame block channel code set in response to determining that a decoding merging receiving end receives the video frame block set to be encoded, determining that each video frame block set to be encoded satisfies the interrupt trigger condition meets the interrupt trigger condition, performing a video frame block staggering process on each video frame block included in the video frame block encoding channel set, performing a video frame decoding process on the video frame block channel set according to the video frame code channel set, and performing a thread splicing process on the video frame code stream to obtain a video frame code stream. In a second aspect, some embodiments of the present disclosure provide a video codec display apparatus, including a splitting unit configured to, in response to determining that an image splitting encoding transmitting end receives video to be encoded, split each video frame to be encoded included in the video to be encoded according to encoding device information of the image splitting encoding transmitting end, to generate a video frame block set to be encoded, and obtain a video frame block set to be encoded; a first determining unit configured to determine a video frame block encoding channel set satisfying an interrupt trigger condition in response to detecting that the video frame block set to be encoded satisfies the interrupt trigger condition, a key vide