CN-121501115-B - Coarse-grained clock management system

CN121501115BCN 121501115 BCN121501115 BCN 121501115BCN-121501115-B

Abstract

The application relates to the technical field of integrated circuit design, in particular to a coarse-granularity clock management system, which transmits a first state signal of a reference module through a third control chain, forms a global state signal by combining a second state signal of an external connection module, controls a core module to enter a clock management starting stage according to a continuous period that the global state signal meets a second preset condition, further changes the core module into a clock closing state, and controls the core module to enter a clock management exiting stage when the core module is in the clock closing state and the global state signal does not meet the second preset condition, further changes the core module into the clock starting state, can control the core module to enter the clock closing state with low power consumption when the core module is idle, effectively reduces the running power consumption of a chip, and can respond to tasks in time when the clock closing state, and recover the core module to be in the clock starting state, thereby having small influence on the running efficiency of the chip.

Inventors

YANG LIKAI

Assignees

沐曦集成电路(上海)股份有限公司

Dates

Publication Date: 20260508
Application Date: 20260113

Claims (8)

1. The coarse-granularity clock management system is characterized by comprising Q third control chains, R external connection modules, a clock management module, RISC-V firmware and hardware, wherein Q and R are positive integers, the Q third control chains comprise S (Q) reference modules, Q is an integer in the range of [1, Q ], the clock management module comprises a period counter, and all the reference modules and all the external connection modules belong to a core module; for any third control chain, the third control chain is used for supporting each reference module in the third control chain to send a first state signal to the clock management module through the third control chain; for any pair of external connection modules, the pair of external connection modules are used for sending a second state signal to the clock management module; Forming global state signals from all first state signals and all second state signals in the clock management module; The period counter is used for counting the number of continuous periods of the global state signal meeting a second preset condition to obtain a period count value; The RISC-V firmware is used for controlling the core module to enter a clock management starting stage when the period count value is equal to a preset period number threshold and the core module is in a clock starting state, and changing the clock starting state into a clock closing state when the clock management starting stage is executed; the hardware is used for controlling the core module to enter a clock management exit stage when the core module is in a clock closing state and the global state signal does not meet a second preset condition, and changing the clock closing state of the core module into a clock opening state when the execution of the clock management exit stage is finished.
2. The coarse-granularity clock management system according to claim 1, wherein for a third control chain of q, the initializing module identifies i=s (q), the first status signal corresponding to the I reference module in the third control chain is used as the I intermediate signal, the I reference module in the third control chain sends the I intermediate signal to the I-1 reference module in the third control chain, the I-1 reference module in the third control chain phase-sums the corresponding I-1 first status signal and the received I intermediate signal to obtain the I-1 intermediate signal, the i=i-1 is updated, the step of sending the I intermediate signal to the I-1 reference module in the third control chain by the I reference module in the third control chain is performed back until i=1, and the I intermediate signal is sent to the clock management module as the chain status signal; Accordingly, the forming global status signals from all the first status signals and all the second status signals includes: The global state signal is formed from all the chain state signals and all the second state signals.
3. The coarse-granularity clock management system of claim 2, wherein the forming the global state signal from all the chain state signals and all the second state signals comprises: all the chain state signals and all the second state signals are phase-ored, and the phase or calculation result is taken as the global state signal.
4. The coarse-grained clock management system of claim 1, wherein the second preset condition is that the global status signal is a second preset value.
5. The coarse-grained clock management system according to claim 1, wherein when the period count value is equal to a preset period count threshold and the core module is in a clock on state, the control of the core module to enter a clock management on phase comprises: When the period count value is equal to a preset period number threshold value and the core module is in a clock starting state, setting a clock management starting interrupt signal from a second preset value to a first preset value; When the first duration time of the clock management on interrupt signal with the first preset value is equal to a first time threshold value, setting a clock off signal with a second preset value to the first preset value by RISC-V firmware; When the second duration of the clock closing signal with the first preset value is equal to a second time threshold value, setting a clock management enabling signal to the first preset value from the second preset value by RISC-V firmware; When the clock management enabling signal is a first preset value, the clocks of the reference modules are configured to be in a closed state, and the external connection modules stop issuing instructions to the reference modules.
6. The coarse-granularity clock management system of claim 5, wherein the clock management on interrupt signal is set from a first preset value to a second preset value when a first duration of the clock management on interrupt signal at the first preset value is less than a first time threshold and the global status signal does not satisfy a second preset condition; When the second duration time of the clock closing signal with the first preset value is smaller than a second time threshold value and the global state signal does not meet the second preset condition, the clock closing signal is set to the first preset value from the second preset value, and the clock management starting interrupt signal is set to the second preset value from the first preset value.
7. The coarse-grain clock management system of claim 5, wherein when the core module is in a clock-off state and the global status signal does not satisfy a second preset condition, controlling the core module to enter a clock management exit phase comprises: When the core module is in a clock closing state and the global state signal does not meet a second preset condition, the hardware sets a clock management starting interrupt signal to a second preset value from a first preset value, and clears a cycle count value of the cycle counter; setting a clock management closing interrupt signal to a first preset value from a second preset value by the hardware; setting, by the RISC-V firmware, the clock management enable signal from a first preset value to a second preset value; When the clock management enabling signal is a second preset value, configuring clocks of all reference modules into an on state, and enabling all external connection modules to start issuing instructions to all reference modules; Setting, by the RISC-V firmware, the clock off signal from a first preset value to a second preset value; the clock management shut down interrupt signal is set by the hardware from a first preset value to a second preset value.
8. The coarse-grained clock management system of claim 7, wherein when the core module is in a clock-off state and the global status signal does not satisfy a second preset condition, the hardware sets the statistics signal from the second preset value to the first preset value; After the clock shutdown signal is set to a second preset value from a first preset value by the RISC-V firmware, the hardware sets a statistics signal from the first preset value to the second preset value, where the statistics signal is used to record the situation that the core module changes back to the clock on state after entering the clock shutdown state.

Description

Coarse-grained clock management system Technical Field The invention relates to the technical field of integrated circuit design, in particular to a coarse granularity clock management system. Background At present, GPU (graphics processor) chips are used as core devices for realizing complex tasks such as graphic rendering and parallel computing, and the performance and the power consumption performance of the GPU chips are paid attention to. With the continuous improvement of the requirements of application scenes on GPU computing capability, the chip integration level is higher and higher, the number and complexity of core modules are continuously increased, and the power consumption problem is increasingly outstanding. Particularly, in the scenes of severe endurance requirements of mobile terminals, portable computing devices and the like, the excessively high power consumption not only limits the service time of the devices, but also can cause chip overheat and frequency reduction, and seriously affects the running stability and user experience of the system. In the architecture system of the GPU chip, the clock management system is a key component for maintaining the normal operation of the chip. The clock signal provides a time sequence reference for each core module in the chip, and the accuracy and the high efficiency of data processing and transmission are ensured. However, the conventional GPU chip clock management system generally adopts a static clock distribution strategy, and whether the core module is in a busy state such as data processing and graphics rendering, or in an idle state waiting for task scheduling, each module always keeps clock signal input, so that the transistor continuously performs charge and discharge operations. Even when the core module has no actual computing task, considerable dynamic power consumption and static power consumption can still be generated, and electric energy waste is caused. Although power consumption optimization means such as dynamic voltage frequency adjustment (DVFS) exist in the prior art, these methods mainly perform voltage and frequency adjustment for the GPU as a whole, and cannot accurately control clock signals of each sub-module in the core module when the core module is idle, so that the operation power consumption of the core module is still higher, and therefore, how to manage clocks of the core module, and further reduce the power consumption of the core module has become a problem to be solved. Disclosure of Invention Aiming at the technical problems, the invention adopts the following technical scheme: A coarse-granularity clock management system comprises Q third control chains, R external connection modules, a clock management module, RISC-V firmware and hardware, wherein Q and R are positive integers, the Q third control chains comprise S (Q) reference modules, Q is an integer in the range of [1, Q ], the clock management module comprises a period counter, and all the reference modules and all the external connection modules belong to a core module. For any third control chain, the third control chain is used for supporting each reference module in the third control chain to send a first state signal to the clock management module through the third control chain. For any pair of external connection modules, the pair of external connection modules is used for sending a second state signal to the clock management module. In the clock management module, a global state signal is formed from all first state signals and all second state signals. The period counter is used for counting the number of continuous periods of the global state signal meeting a second preset condition to obtain a period count value. The RISC-V firmware is used for controlling the core module to enter a clock management starting stage when the period count value is equal to a preset period number threshold and the core module is in a clock starting state, and changing the clock starting state into a clock closing state when the clock management starting stage is executed. The hardware is used for controlling the core module to enter a clock management exit stage when the core module is in a clock closing state and the global state signal does not meet a second preset condition, and changing the clock closing state of the core module into a clock opening state when the execution of the clock management exit stage is finished. Compared with the prior art, the coarse-granularity clock management system provided by the invention has obvious beneficial effects, can achieve quite technical progress and practicality, has wide industrial utilization value, and has at least the following beneficial effects: According to the invention, the first state signal of the reference module is subjected to chain transmission through the third control chain, the second state signal of the external connection module is combined to form a global state signal, the core module is contro