CN-121503356-B - Map mapping method based on accurate synthesis

CN121503356BCN 121503356 BCN121503356 BCN 121503356BCN-121503356-B

Abstract

The application discloses a map mapping method based on accurate synthesis, which comprises the steps of constructing an accurate comprehensive structure library based on NPN equivalence class, inputting a Boolean network, carrying out k-Cut cutting enumeration on the input Boolean network, calculating a truth table, carrying out structure matching in the cutting and the accurate comprehensive structure library through Boolean matching, realizing quick searching by combining NPN classification, generating a coverage network through multi-round mapping optimization, and excavating a logic shared node by combining a structure hash, wherein the multi-round mapping optimization comprises delay guiding mapping, global area topology optimization and local accurate area optimization, generating a new target network based on the optimized coverage network, removing redundant nodes and completing final network construction. According to the application, manual intervention is not required through an automatic mapping and redundancy removing mechanism of the whole process, so that the labor cost of a technical mapping link in chip design is obviously reduced, and the method is particularly suitable for efficient design of complex circuits and emerging most logic base technologies.

Inventors

LI LIN
WANG KE
Zhang Chenlan
Shuai Zhenmian
LV CHEN

Assignees

杭州九之星软件有限公司

Dates

Publication Date: 20260508
Application Date: 20260112

Claims (7)

1. A graph mapping method based on accurate synthesis, comprising: constructing an accurate comprehensive structure library based on NPN equivalence class, and inputting the accurate comprehensive structure library into a Boolean network; Carrying out k-Cut cutting enumeration on an input Boolean network, calculating a truth table, matching the cutting with a structure in an accurate comprehensive structure library through Boolean matching, and realizing quick search by combining NPN classification; Generating an overlay network through multi-round mapping optimization, and mining logic shared nodes by combining structural hash, wherein the multi-round mapping optimization comprises delay guiding mapping, global area topology optimization and local precise area optimization; Generating a new target network based on the optimized coverage network, removing redundant nodes and completing final network construction; the delay-oriented mapping selects cuts according to arrival time, and picks out the cuts meeting delay, including: in the delay directed mapping, the arrival time of the primary input node is initialized to 0; the arrival time of the combined node is the maximum value of the sum of the arrival time of all the inputs and the corresponding input pin delays; for the positive and negative phases of each node, respectively calculating the arrival time of the best matching structure; the global area topology optimization is based on area topology iterative adjustment cutting selection coverage for global area optimization, and comprises the following steps: in global area topology optimization, the area topology is defined as the weighted sum of the area of the node and the area topology of all the precursor nodes according to the fan-out proportion; the area topology is iteratively updated according to the topological reverse order, so that the area topology of the node accurately reflects the contribution of the node to the global area, and the cutting with smaller area topology is prone to be selected, and the global area redundancy is reduced; the local precise area optimization reduces the area through a precise area algorithm, selects optimal cutting coverage, and comprises the following steps: traversing nodes according to a topological sequence by local area optimization; Recursively calculating the exact area for the candidate cuts, comprising: Firstly, calculating the area of a logic gate; and recursively accumulating the area contribution of the leaf nodes according to the reference counts of the leaf nodes, accurately evaluating the newly increased area, and selecting a better cutting area.
2. The graph mapping method based on accurate synthesis according to claim 1, wherein the k-Cut enumeration is performed on the input boolean network and a truth table is calculated, the cuts are matched with structures in the accurate synthesis structure library through boolean matching, and the quick search is realized by combining NPN classification, comprising: Performing cutting enumeration on an input Boolean network according to a topological sequence, reserving k-Cut cutting and minimizing a truth table, and simultaneously considering forward and reverse polarities for Boolean matching so as to optimize logic sharing; Calculating an NPN equivalent class function corresponding to each K-Cut, generating a minimum structure of each NPN class within 5 inputs through an accurate comprehensive tool, and recording parameters of the structure; for each NPN class, multiple alternative structures are stored to address different optimization objectives.
3. The graph mapping method based on exact synthesis of claim 2, wherein the input boolean network Cut enumeration is performed in topological order, preserving k-Cut cuts and minimizing truth tables, boolean matching while considering forward and reverse polarities to optimize logic sharing, comprising: When k-Cut cutting is reserved in cutting enumeration, traversing a network to ensure a topological sequence through a topological view; The cut reservation strategy reserves at most cut_limit cuts for each node, and the truth table of the cuts is minimized according to the sorting of 'size priority and delay times', so that variables without functional support are removed; Forward and reverse polarity matching is performed on the truth table f of each cut, the reverse phase forms of the truth table f are synchronously calculated, matching structures in the library are respectively searched, and logic sharing is achieved.
4. The graph mapping method based on accurate synthesis according to claim 1, wherein generating a new target network based on the optimized overlay network, removing redundant nodes and completing final network construction, comprises: traversing the primary input of the input Boolean network, and creating a corresponding input node in the target network; according to the optimized coverage network, a matched target structure is established for each node according to the topological sequence, and a connection relation among the nodes is established; and executing redundant node removing operation, deleting suspended nodes which are not referenced by the primary output in the target network, and completing the final network construction.
5. The method of graph mapping based on exact synthesis of claim 4, wherein traversing the primary inputs of the input boolean network creates corresponding input nodes in the target network, comprising: For the combined circuit, directly creating nodes consistent with the primary input quantity of the input network, and initializing a fan-out list to be empty; for a sequential circuit, a D trigger node is additionally created, the data input of which is connected with the combinational logic output, the clock input is connected with the global clock signal, and the reset input is connected with the global reset signal, so that the sequential characteristics are consistent with the original network.
6. The graph mapping method based on accurate synthesis according to claim 4, wherein creating a matched target structure for each node in topological order according to the optimized overlay network, and establishing a connection relationship between nodes, comprises: creating nodes strictly according to a topological order, and ensuring that all precursor nodes of the current node are completely created; For each node, invoking a matching supergate according to best cut She Ziji { c1, c2,., ck } connecting the leaf node's output to the supergate's input; If the cutting truth table requires that a certain leaf c2 is in opposite phase, an inverter is inserted between c2 and the super gate; for the sub-structure of the super-gate, the sub-gates are recursively created and connected in a topology defined by the library, leaving the internal structure intact.
7. The graph mapping method based on accurate synthesis according to claim 4, wherein performing a redundant node removal operation to delete dangling nodes in the target network that are not referenced by the primary output, and completing the final network construction, comprises: Starting from the primary output node, traversing all directly or indirectly referenced nodes through a depth-first search, and marking the nodes as valid; Traversing the target network, and deleting all nodes marked as invalid and all input and output edges thereof; checking whether source nodes and target nodes of all edges exist or not, removing suspended edges of which the source nodes or the target nodes are deleted, enabling no invalid connection in network topology, and completing final network construction.

Description

Map mapping method based on accurate synthesis Technical Field The application relates to the technical field of electronic design automation, in particular to a map mapping method based on accurate synthesis. Background In digital integrated circuit design, technology mapping is a key step in converting a technology-independent boolean network (e.g., nand graph, majority voting graph) into a technology-dependent structure (e.g., standard cell, lookup table), directly affecting the area, delay and power consumption performance of the chip. The mapping method of the traditional technology has obvious limitations: On the one hand, the logic sharing capability is not sufficient. The existing method is dependent on single graph representation (such as AIG-based) or fixed cutting strategy, so that sharing potential among different logic structures is difficult to mine, redundant nodes are too many, and area optimization effect is limited. For example, LUT-based mapping tends to lose the shared logic of the original network when the circuit is overlaid, introducing additional nodes after decomposition. On the other hand, global optimization capability is limited. The traditional method mostly adopts a local greedy strategy (such as only optimizing single-node cutting), lacks cooperative consideration of the global area and delay of a circuit, and is easy to fall into local optimum. Meanwhile, the manual design mapping flow needs to adjust parameters aiming at different technical nodes, has low efficiency, and is difficult to adapt to the design requirements of complex circuits and emerging technologies (such as an adiabatic quantum flux parametric superconducting circuit and a quantum dot cellular automaton). Therefore, there is a need for a high-efficiency mapping method that can dynamically integrate multiple graph representation advantages and realize global optimization and logic sharing, so as to break through the performance bottleneck of the conventional method. Disclosure of Invention The application aims to provide a map mapping method based on accurate synthesis, which solves one or more technical problems in the prior art and at least provides a beneficial selection or creation condition. The application adopts the following technical scheme for realizing the purposes of the application: the application provides a map mapping method based on accurate synthesis, which comprises the following steps: constructing an accurate comprehensive structure library based on NPN equivalence class, and inputting the accurate comprehensive structure library into a Boolean network; Carrying out k-Cut cutting enumeration on an input Boolean network, calculating a truth table, matching the cutting with a structure in an accurate comprehensive structure library through Boolean matching, and realizing quick search by combining NPN classification; Generating an overlay network through multi-round mapping optimization, and mining logic shared nodes by combining structural hash, wherein the multi-round mapping optimization comprises delay guiding mapping, global area topology optimization and local precise area optimization; And generating a new target network based on the optimized coverage network, removing redundant nodes and completing final network construction. Further, carrying out k-Cut cutting enumeration on an input Boolean network, calculating a truth table, matching the cutting with a structure in an accurate comprehensive structure library through Boolean matching, and realizing quick searching by combining NPN classification, wherein the method comprises the following steps: Performing cutting enumeration on an input Boolean network according to a topological sequence, reserving k-Cut cutting and minimizing a truth table, and simultaneously considering forward and reverse polarities for Boolean matching so as to optimize logic sharing; Calculating an NPN equivalent class function corresponding to each K-Cut, generating a minimum structure of each NPN class within 5 inputs through an accurate comprehensive tool, and recording parameters of the structure; for each NPN class, multiple alternative structures are stored to address different optimization objectives. Further, performing the input boolean network Cut enumeration in topological order, preserving k-Cut cuts and minimizing truth tables, boolean matching while considering forward and reverse polarities to optimize logic sharing, comprising: When k-Cut cutting is reserved in cutting enumeration, traversing a network to ensure a topological sequence through a topological view; The cut reservation strategy reserves at most cut_limit cuts for each node, and the truth table of the cuts is minimized according to the sorting of 'size priority and delay times', so that variables without functional support are removed; Forward and reverse polarity matching is performed on the truth table f of each cut, the reverse phase forms of the truth table f are synchronously