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CN-121510881-B - Wafer processing method and semiconductor device

CN121510881BCN 121510881 BCN121510881 BCN 121510881BCN-121510881-B

Abstract

A wafer processing method and a semiconductor device includes providing a wafer bonding structure to be processed, performing a first edge trimming to remove at least an edge portion of a second wafer, the first edge trimming having a width smaller than a preset trimming width, performing a polishing thinning process to thin a second bottom support layer, performing an etching process to remove a remaining portion of the second bottom support layer, performing a second edge trimming, a total width of the second edge trimming and the first edge trimming reaching a preset trimming width, a depth of the second edge trimming extending from a second intermediate dielectric layer to pass through a first top device layer, and removing the second intermediate dielectric layer, so that by performing the edge trimming in stages and controlling the width and depth of each edge trimming, portions where multi-steps and dishing problems may occur are removed, and a product yield is improved while an influence on an overall process is small, under a condition that a total trimming width is unchanged.

Inventors

  • Jiang Hannie

Assignees

  • 芯联越州集成电路制造（绍兴）有限公司

Dates

Publication Date
20260512
Application Date
20251224

Claims (10)

  1. 1. A method of processing a wafer, the method comprising: providing a wafer bonding structure to be processed, the wafer bonding structure comprising a first wafer and a second wafer, the first wafer comprising a first bottom support layer, a first intermediate dielectric layer and a first top device layer between a first bottom surface and a first top surface, the second wafer comprising a second bottom support layer, a second intermediate dielectric layer and a second top device layer between a second bottom surface and a second top surface, the first wafer and the second wafer being bonded to each other with the first top surface facing the second top surface; performing a first edge trimming with the second bottom surface side as a process execution side to remove at least an edge portion of the second wafer, the edge portion being a portion of the second wafer projected in a direction perpendicular to the second top surface beyond the projection of the second top device layer, the first edge trimming having a width less than a preset trimming width; performing a grinding thinning process to thin the second bottom support layer; performing an etching process to remove the remaining portion of the second bottom support layer; performing a second edge trim, the total width of the second edge trim and the first edge trim reaching the preset trim width, the depth of the second edge trim extending from the second intermediate dielectric layer to through the first top device layer; And removing the second intermediate dielectric layer.
  2. 2. The wafer processing method of claim 1, wherein the second edge trim has a width that is less than a width of the first edge trim.
  3. 3. The wafer processing method according to claim 2, wherein a width of the second wafer edge trim is 1/6 or less of a width of the first wafer edge trim.
  4. 4. The wafer processing method of claim 1, wherein a distance between a stop position of the second edge conditioner and the first bottom surface is smaller than a distance between a stop position of the first edge conditioner and the first bottom surface in a direction perpendicular to the second top surface.
  5. 5. The wafer processing method of claim 1, wherein a distance between a stop location of the second edge trim and the first bottom surface in a direction perpendicular to the second top surface is less than a thickness of the first bottom support layer.
  6. 6. The method of claim 1, wherein, The depth of the first edge trim extends from the second bottom surface to inside the first top device layer; The second crystal edge trimming stop position is located on a first surface or a second surface or between the first surface and the second surface, wherein the first surface is a surface of the first intermediate dielectric layer facing the first top device layer, and the second surface is a surface of the first bottom support layer facing the first intermediate dielectric layer.
  7. 7. The method of claim 6, wherein a distance between a stop position of the first edge trim and a surface of the first top device layer facing the first intermediate dielectric layer in a direction perpendicular to the second top surface is less than or equal to a thickness of a remaining portion of the second bottom support layer after performing the polish-thinning process.
  8. 8. The wafer processing method of claim 1, wherein the second wafer edge trim employs a ramp trim process.
  9. 9. The method of claim 8, wherein the first edge trimming is performed using a right angle trimming process.
  10. 10. A semiconductor device manufactured by a manufacturing method of a semiconductor device comprising the steps of the wafer processing method according to any one of claims 1 to 9.

Description

Wafer processing method and semiconductor device Technical Field The present application relates to the field of semiconductor technology, and in particular, to a wafer processing method and a semiconductor device. Background In a Bonding wafer (Bonding wafer) process, a wafer edge trimming (TRIMMING EDGE) technology is used to cut off the irregular, uneven or unstable bonded area of the outer ring of the bonded wafer, so as to improve the yield and product reliability of the subsequent process. Taking Micro Electro MECHANICAL SYSTEM, MEMS as an example, the bonding process of a silicon on insulator (Silicon On Insulator, SOI) wafer generally includes multiple times of bonding process, and crystal edge trimming, grinding thinning (polishing) and maskless etching (blank ET) processes are sequentially performed after each time of bonding to remove the supporting layer, wherein by performing crystal edge trimming first, the crystal edge region with weak bonding is removed in advance, so that the problems of breaking or cracking in the subsequent process can be avoided. It can be seen that edge trimming also has the effect of providing for performing polish thinning and maskless etching processes. In an ideal situation, the side surface of the wafer bonding structure is subjected to crystal edge trimming, grinding thinning and maskless etching, and the whole appearance is flat and smooth. However, in the actual process, after the maskless etching process is performed, the phenomenon that multiple steps and concave parts occur in the crystal edge area is detected, so that defects at the crystal edge are accumulated, the defects become sources of defects in the subsequent process, and the product yield is reduced. Disclosure of Invention Accordingly, embodiments of the present application provide a wafer processing method and a semiconductor device to solve at least one of the problems in the background art. In a first aspect, an embodiment of the present application provides a wafer processing method, where the method includes: providing a wafer bonding structure to be processed, the wafer bonding structure comprising a first wafer and a second wafer, the first wafer comprising a first bottom support layer, a first intermediate dielectric layer and a first top device layer between a first bottom surface and a first top surface, the second wafer comprising a second bottom support layer, a second intermediate dielectric layer and a second top device layer between a second bottom surface and a second top surface, the first wafer and the second wafer being bonded to each other with the first top surface facing the second top surface; performing a first edge trimming with the second bottom surface side as a process execution side to remove at least an edge portion of the second wafer, the edge portion being a portion of the second wafer projected in a direction perpendicular to the second top surface beyond the projection of the second top device layer, the first edge trimming having a width less than a preset trimming width; performing a grinding thinning process to thin the second bottom support layer; performing an etching process to remove the remaining portion of the second bottom support layer; performing a second edge trim, the total width of the second edge trim and the first edge trim reaching the preset trim width, the depth of the second edge trim extending from the second intermediate dielectric layer to through the first top device layer; And removing the second intermediate dielectric layer. In combination with the first aspect of the present application, in an alternative embodiment, the second crystal edge trim has a width that is smaller than a width of the first crystal edge trim. In an alternative embodiment, in combination with the first aspect of the present application, the width of the second edge trim is less than 1/6 of the width of the first edge trim. With reference to the first aspect of the present application, in an alternative embodiment, a distance between a stop position of the second edge conditioner and the first bottom surface is smaller than a distance between a stop position of the first edge conditioner and the first bottom surface in a direction perpendicular to the second top surface. In an alternative embodiment, in combination with the first aspect of the present application, the distance between the stop location of the second edge trim and the first bottom surface in a direction perpendicular to the second top surface is less than the thickness of the first bottom support layer. In combination with the first aspect of the application, in an alternative embodiment, The depth of the first edge trim extends from the second bottom surface to inside the first top device layer; The second crystal edge trimming stop position is located on a first surface or a second surface or between the first surface and the second surface, wherein the first surface is a surface of the first in