CN-121522421-B - PCB flying probe test path optimization method based on electrical characteristics

CN121522421BCN 121522421 BCN121522421 BCN 121522421BCN-121522421-B

Abstract

The invention relates to the technical field of probe testing, in particular to a PCB flying probe testing path optimization method based on electrical characteristics, which comprises the steps of calculating accessibility scores of test points according to the distribution of board test points and elements to determine risk types of the test points, and determining risk area grades corresponding to grid units according to the accessibility scores and potential shadow areas; the method comprises the steps of optimizing a test path of a probe according to a risk zone grade corresponding to a grid unit, adjusting initial movement speeds of the test path of the probe in different grid units, determining overlapped grids according to initial probe angles and test paths corresponding to the probes aiming at the same movement time sequence of different probe groups, determining whether collision risks exist among the probes according to the initial movement speeds of the probes in different grid units, and taking corresponding adjustment measures according to the number of the overlapped grids when the collision risks exist among the probes. The invention combines multidimensional optimization test paths based on the electrical characteristics of the board and testability design.

Inventors

LONG MANSHENG
WANG HONGGUANG
LIU YUAN
GUI HAILONG
WANG KUNLIN
LI HONGJUN

Assignees

井冈山大学

Dates

Publication Date: 20260508
Application Date: 20251105

Claims (10)

1. The PCB flying probe test path optimization method based on the electrical characteristics is characterized by comprising the following steps of: identifying each grid cell divided according to the initial resolution based on the grid cell labeling value and the test parameters of the probes, so as to determine the initial probe angle corresponding to the test points in each grid cell based on the interval distance between the identification results and the simultaneous test points; acquiring adjacent intervals among a plurality of test points to determine the density types of the test points so as to merge corresponding grid cells, and dividing the area types based on the distribution condition of the plurality of test points in the grid cells so as to determine the test sequence of the probe group to the plurality of test points; determining a probe set test moving method according to whether the test points have a ground detection requirement or not, and correspondingly adjusting a judging standard of whether the test points of the probe set are conducted or not based on the board contamination area identification condition of the board image; obtaining accessibility scores of a plurality of test points based on the distribution of the test points and the elements of the board surface so as to combine the identification results of the grid units to determine the grade of the risk area corresponding to each grid unit; optimizing a test path of the probe based on the risk zone grade corresponding to each grid cell and adjusting the initial moving speed corresponding to the grid cell where the optimized test path of the probe is located by combining the accessibility score; Determining overlapping grids based on initial probe angles and test paths corresponding to probes for the same movement time sequence of different probe groups so as to determine whether collision risks exist among the probes in combination with initial movement speeds of the probes corresponding to all grid units; And responding to collision risks among the probes, and determining initial probe angle or movement parameters corresponding to the adjusting probes according to the number of the overlapped grids.
2. The method of optimizing a PCB flying probe test path based on electrical characteristics of claim 1, wherein the identifying each grid cell divided by the initial resolution comprises: the simulated probe approaches the board surface at the initial probe angle, the coordinates of the test point are taken as the center, and in a rectangular area taking the probe arm diameter and the initial probe angle of the probe as parameters, if grid cells with higher heights than the grid cells where the test point is located exist, the grid cells in the rectangular area are marked as potential shadow areas.
3. The method for optimizing a PCB flying probe test path based on electrical characteristics of claim 2, wherein determining an initial probe angle corresponding to a test point in each grid cell comprises: When the probe moves to the test point of the grid unit in the potential shadow area, increasing the initial probe angle according to the labeling value of the grid unit in the rectangular area, and reducing the initial probe angle corresponding to the probe according to the theoretical interval distance of the test point which cannot be in the same measurement time sequence.
4. The method of optimizing a PCB flying probe test path based on electrical characteristics of claim 3, wherein the process of determining the test sequence of the probe set for the plurality of test points comprises: Calculating the adjacent distances between the plurality of test points and the adjacent test points according to the coordinates of the plurality of test points; when the adjacent distance is smaller than the minimum density evaluation threshold, judging that the test point and the adjacent test point are high-density test points, and merging the corresponding test point with the grid unit where the adjacent test point is located; Dividing an area consisting of a plurality of grids containing all high-density test points into a high-density area, and dividing an area consisting of the rest connected grid units into a low-density area; The test order priority of the high density region is greater than the test order priority of the low density region.
5. The method for optimizing the PCB flying probe test path based on the electrical characteristics according to claim 4, wherein the pixel level difference operation is performed on the image of the grid unit where the test point is located and the reference image, and if the difference value of the area difference comparison result of the grid image is larger than the difference value, the test point is judged to be located in the plate surface dirty area.
6. The method of optimizing a PCB flying probe test path based on electrical characteristics according to claim 5, wherein the process of adjusting the decision criteria for whether the probe set measurement test point is conductive comprises: if the test point is in the plate surface contamination area, changing the resistance threshold value to be a threshold value range; When the measured value is lower than the threshold range, judging that the test point is conducted and the line connection is good; When the measured value exceeds the threshold range, judging that the test points are open, and disconnecting the lines between the test points; And when the measured value is in the threshold range, judging that the measured value of the test point is influenced by the surface offset, and connecting a circuit well or opening a circuit slightly.
7. The method for optimizing a PCB flying probe test path based on electrical characteristics of claim 6, wherein determining the risk zone level for each grid cell comprises: Defining a circular analysis area according to a specific radius by taking the test points as circle centers, and calculating accessibility scores of a plurality of test points according to distribution parameters of elements in the area; When the shadow region risk factor is one or the accessibility score is smaller than or equal to the accessibility first threshold value, judging that the grid cells are blocked or extremely crowded by elements, and marking the grid cells as high risk regions; When the shadow region risk factor is zero and the accessibility score is larger than the accessibility first threshold value and smaller than the accessibility second threshold value, judging that the grid unit is not shielded but is in space constraint, and marking the grid unit as a risk region; And when the shadow region risk factor is zero and the accessibility score is greater than or equal to the accessibility second threshold value, judging that the grid cells are open and easy to access, and marking the grid cells as low risk regions.
8. The method for optimizing the PCB flying probe test path based on the electrical characteristics according to claim 7, wherein the total moving cost of the grid unit is calculated according to the risk zone level where the grid unit is located by setting the risk cost, and the total moving cost is a moving reference value of the test path; the probe moves according to the initial moving speed in the low risk area, the initial moving speed is reduced according to the ratio of the accessibility score to the accessibility second threshold in the risk area, and the initial moving speed is reduced according to the ratio of the accessibility score to the accessibility first threshold in the high risk area.
9. The method of optimizing a PCB flying probe test path based on electrical characteristics of claim 8, wherein the process of determining the overlapping grid comprises: Acquiring initial probe angles corresponding to probes of different probe groups in the same moving time sequence, determining a plurality of grid cells through which the probes project, and determining overlapping grids according to whether the grid cells are overlapped or not; For a plurality of overlapped grid units, determining time difference of probes of different probe groups passing through overlapped grids, and judging collision risk among the probes when the time difference is smaller than or equal to a critical time difference; And when the time difference is larger than the critical time difference, judging that collision risk does not exist between the probes.
10. The method for optimizing a PCB flying probe test path based on electrical characteristics according to claim 9, wherein when collision risk exists between probes, corresponding adjustment measures are adopted according to the number of overlapped grids; when the ratio of the number of overlapped grids to the number of grids occupied by the projection of the probes of different probe groups is smaller than a projection duty ratio threshold value and the initial probe angle corresponding to the probe is larger than a standard angle, judging that the collision risk between the probes is lower, and adjusting the initial probe angle corresponding to the probe; and when the ratio of the number of the overlapped grids to the number of grids occupied by the projection of the probes of different probe groups is greater than or equal to a projection duty ratio threshold, or the initial probe angle corresponding to the overlapped grids is greater than or equal to a standard angle, regulating the moving path or moving time sequence of any probe.

Description

PCB flying probe test path optimization method based on electrical characteristics Technical Field The invention relates to the technical field of probe testing, in particular to a PCB flying probe testing path optimization method based on electrical characteristics. Background The flying probe test is a PCB electrical test technology without manufacturing a special needle bed fixture, and the electrical characteristics of short circuit, open circuit, element value and the like of the PCB are verified by controlling a plurality of precision probes to move and contact with test points. The method is widely applied to PCB prototype verification, small-batch production and high-reliability product test. The test efficiency of the flying probe tester directly depends on the planning quality of the probe moving path. The goal of path planning is to minimize the total test time, which is mainly composed of the idle movement time and the test switching time of the probe, on the premise of ensuring the test coverage. Currently, the main method for optimizing the flying probe test path in the prior art mainly focuses on the geometric path planning level, and the core is to abstract the problem into one traveler problem (TSP) or multiple travelers problem (mTSP). The Chinese patent publication No. CN117890766A discloses a path optimization method of a two-layer structure type flying needle tester based on clustering, which comprises the following steps that S1, network data are imported from a network provided with test points, the network is divided into a single-sided network or a double-sided network according to whether the test points are arranged on one side or two sides of a PCB (printed circuit board), and then, the linkage mode of flying needles is determined according to the number of the test points on the single-sided network or the double-sided network, wherein the flying needles comprise left flying needles and right flying needles; the method comprises the steps of S2, clustering all networks on a PCB by using a DBSCAN algorithm, calculating the central coordinate of each cluster, determining clusters which the flying needle needs to pass when testing connectivity of the PCB, S3, calculating shortest distance point pairs among different clusters by using a double pointer method, taking the shortest distance point pairs as inter-cluster distances, S4, determining the cluster detection sequence of the flying needle for different clusters by using a preset first algorithm, S5, determining the test point detection sequence of the test point inside each cluster by using a preset second algorithm, S6, dividing a path by taking the network as a limit to obtain a moving path of the flying needle, S7, judging whether the moving path causes collision between the left flying needle and the right flying needle, returning to the step S6 if not, and outputting the moving path as a path optimization result. Therefore, the path optimization method of the two-layer structure type flying probe tester based on clustering has the following problems: considering test points as abstract geometric points, the optimization goal is only to minimize the total travel distance, however, the nature of PCB testing is electrical verification, and the collaboration, sequence of probes is inherently constrained and required by different electrical networks and test types (e.g., conductive, insulating, four-wire measurement). The existing planning cannot understand the electrical principles such as star test, common ground test and the like, so that a large number of unnecessary probes are moved and switched, and the efficiency cannot be improved from the root of the test logic; the physical characteristics such as the layout of the PCB, the height of the element, accessibility of the test points and the like are not fully considered in path planning, and for a high-density board or a board with high and large element shielding, the planned path can not be executed, and the obstacle avoidance is performed by manual intervention, so that the engineering complexity is increased. Disclosure of Invention Therefore, the invention provides an optimization method of a PCB flying probe test path based on electrical characteristics, which is used for solving the problems that the optimization dimension of the electrical characteristics is single and the electrical characteristics are out of joint with the design under test in the prior art. In order to achieve the above object, the present invention provides a PCB flying probe test path optimization method based on electrical characteristics, including: dividing a plate surface into a plurality of grid cells according to an initial resolution, identifying the grid cells in a potential shadow area according to grid cell labeling values and test parameters of probes, and determining initial probe angles corresponding to test points in the grid cells by combining the interval distances between the