Search

CN-121530522-B - Pin multiplexing structure of OLT (optical line terminal) equipment

CN121530522BCN 121530522 BCN121530522 BCN 121530522BCN-121530522-B

Abstract

The invention discloses a pin multiplexing structure of OLT equipment, which comprises a TIA module and a LA module, wherein the TIA module is provided with a burst RSSI monitoring unit, a PD unit, a TIA unit, a comparator unit and a RESET-IN/RSSI-OUT pin, the LA module is provided with a logic switching unit, a current-to-voltage unit, a RESET-OUT/RSSI-IN pin, a system RESET port and a system RSSI port, and the RESET-OUT/RSSI-IN pin is connected with the RESET-IN/RSSI-OUT pin. Compared with the prior art, the invention can effectively reduce the number of pins and reduce the packaging cost.

Inventors

  • CHEN WEI
  • LI YIHONG
  • ZHOU JIE
  • LIN SHAOHENG
  • ZHANG KEXUN

Assignees

  • 厦门优迅芯片股份有限公司

Dates

Publication Date
20260508
Application Date
20260115

Claims (8)

  1. 1. The pin multiplexing structure of the OLT equipment is characterized by comprising a TIA module and a LA module; The TIA module is provided with a burst RSSI monitoring unit, a PD unit, a TIA unit, a comparator unit and a RESET-IN/RSSI-OUT pin, wherein the input end of the burst RSSI monitoring unit is connected with the negative electrode of the PD unit, the output end of the burst RSSI monitoring unit is connected with the RESET-IN/RSSI-OUT pin, and the burst RSSI monitoring unit is used for forming corresponding I RESET current signal output according to the power of the PD unit; The LA module comprises a logic switching unit, a current-to-voltage unit, a RESET-OUT/RSSI-IN pin, a system RESET port and a system RSSI port, wherein the system RESET port is used for accessing a RESET signal sent by a system, the system RSSI port is used for receiving an RSSI-Trigger signal sent by the system, the logic switching unit comprises a first switch, a second switch, a first NOT gate, a second NOT gate and a first AND gate, the first end of the first switch and the first end of the second switch are connected with the RESET-OUT/RSSI-IN pin, the second end of the first switch is connected with the output end of the first NOT gate, the control end of the first switch and the input end of the second NOT gate are connected with the system RESET port, the output end of the second NOT gate is connected with the input end of the first AND gate, the output end of the first AND gate is connected with the control end of the second switch, the second end of the second switch is connected with the input end of the current-to-voltage unit, the current-to-output voltage signal conversion of I RESET is used for converting the current signal into a V RESET signal and a RESET signal which is not used for converting the same phase signal; The RESET-OUT/RSSI-IN pin of the LA module is connected to the RESET-IN/RSSI-OUT pin of the TIA module.
  2. 2. The pin multiplexing structure of the OLT equipment according to claim 1, wherein the current-to-voltage unit comprises a conversion resistor and an analog-to-digital conversion circuit, a first end of the conversion resistor and an input end of the analog-to-digital conversion circuit are connected with an input end of the current-to-voltage unit, and a second end of the conversion resistor is grounded.
  3. 3. The pin multiplexing structure of claim 2, wherein the LA module further comprises a current limiting protection unit connected in parallel with the switching resistor.
  4. 4. The pin multiplexing structure of the OLT equipment according to claim 3, wherein the current limiting protection unit comprises a current limiting switch, a current limiting circuit, an RSSI Delay circuit and a digital logic circuit, the first end of the current limiting circuit is connected with the first end of the converting resistor, the second end of the current limiting circuit is connected with the first end of the current limiting switch, the second end of the current limiting switch is connected with the second end of the converting resistor, the control end of the current limiting switch is connected with the digital logic circuit, the digital logic circuit is connected with a RESET port, the digital logic circuit is connected with the RSSI port of the system through the RSSI Delay circuit, the RSSI Delay circuit is used for carrying out Delay processing on an RSSI-Trigger signal to obtain an RSSI-Trigger-Delay signal, the Delay time of the RSSI Delay circuit is smaller than the pulse width of the RSSI-Trigger-Delay signal, the digital logic circuit closes the current limiting switch when the rising edge of the RSSI-Trigger-Delay signal is monitored, and the digital logic circuit opens the current limiting switch when the rising edge of the RESET signal is monitored.
  5. 5. A pin multiplexing structure of an OLT device according to claim 4, wherein said current limiting circuit comprises at least two current limiting diodes connected in series.
  6. 6. The pin multiplexing structure of claim 4, wherein the digital logic circuit comprises a RESET delay circuit, a signal compression circuit, an OR gate and a D flip-flop; The input end of the RESET delay circuit and the D pin of the D trigger are connected with the first input end of the digital logic circuit, the input end of the signal compression circuit is connected with the second input end of the digital logic circuit, the output end of the RESET delay circuit and the output end of the signal compression circuit are respectively connected with the two input ends of the OR gate, the output end of the OR gate is connected with the CLK pin of the D trigger, and the Q pin of the D trigger is connected with the output end of the digital logic circuit; The first input end of the digital logic circuit is connected with a system RESET port to be accessed to a RESET signal, the second input end of the digital logic circuit is connected with the output end of the RSSI Delay circuit to be accessed to an RSSI-Trigger-Delay signal, the output end of the digital logic circuit is connected with the control end of the current-limiting switch, and the output end of the digital logic circuit outputs a CK signal to control the switch of the current-limiting switch; The RESET Delay circuit is used for carrying out Delay processing on the RESET signal to obtain a RESET-Delay signal, the Delay time of the RESET Delay circuit is smaller than the pulse width of the RESET signal, the signal compression circuit is used for compressing the RSSI-Trigger-Delay signal to obtain an RSSI-Trigger-Delay-Rise signal, the rising edge time of the RSSI-Trigger-Delay-Rise signal is the same as the rising edge time of the RSSI-Trigger-Delay signal, and the pulse width of the RSSI-Trigger-Delay-Rise signal is smaller than the pulse width of the RSSI-Trigger-Delay signal.
  7. 7. The pin multiplexing structure of the OLT equipment according to claim 6, wherein the signal compression circuit comprises a signal Delay circuit, an exclusive-OR gate and a second AND gate, the input end of the signal Delay circuit, the first input end of the exclusive-OR gate and the first input end of the second AND gate are connected with the input end of the signal compression circuit, the output end of the signal Delay circuit is connected with the second input end of the exclusive-OR gate, the output end of the second AND gate is connected with the output end of the signal compression circuit, the signal Delay circuit is used for carrying out Delay processing on an RSSI-Trigger-Delay signal, and the Delay time of the signal Delay circuit is smaller than the pulse width of the RSSI-Trigger-Delay signal.
  8. 8. The pin multiplexing structure of the OLT equipment according to claim 1, wherein the burst RSSI monitoring unit comprises a first MOS tube and a second MOS tube, the drain electrode and the grid electrode of the first MOS tube and the grid electrode of the second MOS tube are connected with the input end of the burst RSSI monitoring unit, the source electrode of the first MOS tube and the source electrode of the second MOS tube are grounded, and the drain electrode of the second MOS tube is connected with the output end of the RSSI monitoring unit.

Description

Pin multiplexing structure of OLT (optical line terminal) equipment Technical Field The invention relates to the field of optical communication, in particular to a pin multiplexing structure of an OLT device. Background The receiving end of the conventional OLT (Optical LINE TERMINAL) is burst receiving, and in order to meet the burst timing, the system is required to send RESET signals to a TIA (Trans-IMPEDANCE AMPLIFIER, transimpedance amplifier) module and a LA (LIMITING AMPLIFIER ) module to achieve circuit convergence, so that the TIA module and the LA module both need to set RESET pins. In addition, if the system is to monitor the optical power of a PD (PhotoDiode) unit in the TIA module, the system needs to send an RSSI-Trigger signal to the TIA module and the LA module, so that the TIA module and the LA module perform RSSI monitoring, but in this way, both the TIA module and the LA module need to increase an RSSI pin, which increases the packaging cost. In view of the above problems, it is necessary to study a pin multiplexing structure of OLT equipment, so as to solve the problems of the prior art, such as a large number of pins and high packaging cost. Disclosure of Invention The invention aims to provide a pin multiplexing structure of an OLT device, which aims to solve the problems of high pin number and high packaging cost in the prior art. In order to achieve the above object, the solution of the present invention is: A pin multiplexing structure of an OLT device comprises a TIA module and a LA module; the TIA module is provided with a burst RSSI monitoring unit, a PD unit, a TIA unit, a comparator unit and RESET-IN/RSSI-OUT pins; the input end of the TIA unit is connected with the output end of the comparator unit, the second input end of the comparator unit is connected with the Vref threshold signal, the LA module is provided with a logic switching unit, a current switching voltage unit, a RESET-OUT/RSSI-IN pin, a system RESET port and a system RSSI port, the system RESET port is used for accessing the RESET signal sent by the system, the system RSSI port is used for receiving the RSSI-Trigger signal sent by the system, the logic switching unit comprises a first switch, a second switch, a first NOT gate, a second NOT gate and a first AND gate, the first end of the first switch is connected with the RESET-OUT/RSSI pin, the second end of the first switch is connected with the first output end of the first switch, the second end of the first switch is connected with the first NOT gate, the second end of the second switch is connected with the second AND gate, the first end of the second switch is connected with the first NOT gate, the second end of the second switch is connected with the second NOT gate is connected with the second AND gate, the current-to-voltage unit is used for converting an IRESET current signal into a VRESET voltage signal, the first NOT gate and the second NOT gate are used for converting the RESET signal into an IN-phase RESET-SW signal, and the RESET-OUT/RSSI-IN pin of the LA module is connected with the RESET-IN/RSSI-OUT pin of the TIA module. The current-to-voltage unit comprises a conversion resistor and an analog-to-digital conversion circuit, wherein the first end of the conversion resistor and the input end of the analog-to-digital conversion circuit are connected with the input end of the current-to-voltage unit, and the second end of the conversion resistor is grounded. The LA module also comprises a current limiting protection unit connected with the conversion resistor in parallel. The current limiting protection unit comprises a current limiting switch, a current limiting circuit, an RSSI Delay circuit and a digital logic circuit, wherein the first end of the current limiting circuit is connected with the first end of a conversion resistor, the second end of the current limiting circuit is connected with the first end of the current limiting switch, the second end of the current limiting switch is connected with the second end of the conversion resistor, the control end of the current limiting switch is connected with the digital logic circuit, the digital logic circuit is connected with a system RESET port, the digital logic circuit is connected with the system RSSI port through the RSSI Delay circuit, the RSSI Delay circuit is used for carrying out Delay processing on an RSSI-Trigger signal to obtain an RSSI-Trigger-Delay signal, the Delay time of the RSSI Delay circuit is smaller than the pulse width of the RSSI-Trigger-Delay signal, the digital logic circuit closes the current limiting switch when the rising edge of the RSSI-Trigger-Delay signal is monitored, and the digital logic circuit opens the current limiting switch when the rising edge of the RESET signal is monitored. The current limiting circuit includes at least two current limiting diodes connected in series. The digital logic circuit comprises a RESET Delay circuit, a signal compression circu