Search

CN-121531981-B - Semiconductor device test structure and semiconductor device evaluation method using the same

CN121531981BCN 121531981 BCN121531981 BCN 121531981BCN-121531981-B

Abstract

The invention provides a semiconductor device test structure and a semiconductor device evaluation method using the same, wherein the semiconductor device test structure comprises a resistance measurement line, a capacitance measurement line and a dummy line, the resistance measurement line and the capacitance measurement line are arranged on a semiconductor substrate in the same layer, and the resistance measurement line is used for measuring the resistance of a connecting line; the capacitance measuring line is used for measuring the capacitance of the connecting line, the capacitance measuring line comprises a first capacitance measuring line and a second capacitance measuring line, the first capacitance measuring line and the second capacitance measuring line are respectively arranged on two sides of the resistance measuring line, the dummy line is arranged on the adjacent layers of the resistance measuring line and the capacitance measuring line, and accurate measurement of the resistance and the capacitance in the semiconductor device connecting line structure is realized by the same test structure.

Inventors

  • Jing Kouxue

Assignees

  • 合肥晶合集成电路股份有限公司

Dates

Publication Date
20260512
Application Date
20260114

Claims (8)

  1. 1. The semiconductor device testing structure is characterized by comprising a resistance measuring line, a capacitance measuring line and a dummy line, wherein the resistance measuring line and the capacitance measuring line are arranged on a semiconductor substrate in the same layer, the resistance measuring line is used for measuring the resistance of a connecting line, the capacitance measuring line is used for measuring the capacitance of the connecting line, the capacitance measuring line comprises a first capacitance measuring line and a second capacitance measuring line, the first capacitance measuring line and the second capacitance measuring line are respectively arranged on two sides of the resistance measuring line, and the dummy line is arranged on adjacent layers of the resistance measuring line and the capacitance measuring line and is grounded or applied with a preset voltage.
  2. 2. The semiconductor device testing structure of claim 1, wherein the first and second capacitance measurement lines each comprise a plurality of comb-like connection lines such that the first and second capacitance measurement lines are each in a comb-like pattern.
  3. 3. The semiconductor device testing structure of claim 2, wherein the capacitance measuring lines comprise two first capacitance measuring lines and two second capacitance measuring lines, the two first capacitance measuring lines are inserted relatively, the two second capacitance measuring lines are inserted relatively, the two first capacitance measuring lines and the two second capacitance measuring lines are connected with four measuring ends, and the four measuring ends are used for four-endpoint resistance measurement.
  4. 4. The semiconductor device test structure of claim 1, wherein the dummy lines comprise first dummy lines and/or second dummy lines, the first dummy lines being provided in lower layers of the resistance measurement lines and the capacitance measurement lines, and/or the second dummy lines being provided in upper layers of the resistance measurement lines and the capacitance measurement lines.
  5. 5. The semiconductor device testing structure of claim 4, further comprising a third dummy line disposed in an adjacent region outside of the first and second capacitance measurement lines.
  6. 6. A semiconductor device evaluation method using the semiconductor device test structure according to any one of claims 1 to 5, comprising the steps of: using a resistance measuring line to perform four-endpoint resistance measurement; and using the resistance measurement line and the capacitance measurement line to measure lateral capacitance and vertical capacitance, wherein the lateral capacitance is lateral electrostatic capacitance between connecting lines in the capacitance measurement line, and the vertical capacitance is vertical electrostatic capacitance between one of comb patterns of the capacitance measurement line and connecting lines in the dummy line.
  7. 7. The method for evaluating a semiconductor device according to claim 6, wherein, By switching the potentials of the resistance measurement line, the first dummy line and the second dummy line, two different capacitance measurement states are formed: in a first measurement state, grounding the resistance measurement line, the first dummy line, and the second dummy line; In a second measurement state, connecting the resistance measurement line, the first dummy line and the second dummy line to a predetermined potential; measuring a first combined value of the lateral capacitance and the vertical capacitance in the first measurement state; measuring a second combined value of the lateral capacitance and the vertical capacitance in the second measurement state; the lateral capacitance and the vertical capacitance are calculated based on the first combined value and the second combined value.
  8. 8. The method for evaluating a semiconductor device according to claim 7, wherein the lateral capacitance Cl and the vertical capacitance Cv are calculated by: Cl=(Cap2-Cap1)/2; Cv=(Cap1- (Nf-1)×2×Cl)/(2×Nf); Wherein Cap1 is a first combination value, cap2 is a second combination value, and Nf is the number of teeth of each comb pattern in the capacitance measuring line.

Description

Semiconductor device test structure and semiconductor device evaluation method using the same Technical Field The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device testing structure and a semiconductor device evaluation method using the same. Background By requiring evaluation/verification of semiconductor devices and their process conditions using semiconductor device test structures, such structures are not directly related to actual circuit functions, and are designed to be able to measure specific physical quantities and electrical characteristics. Such test structures are also referred to as test vectors (TEST PATTERN) or test chips. Currently, the resistance and capacitance are measured separately by different test structures. As shown in fig. 1-2, the test structure for resistance measurement is composed of a resistance measurement line 10 and a dummy line 12, and as shown in fig. 3-4, the test structure for capacitance measurement is composed of a capacitance measurement line 14 and a dummy line 16 constituting a comb pattern. However, when the measurement of the resistance and the capacitance is performed by using different test structures, respectively, even if the connection lines as the measurement targets have the same line width and pitch, agreement cannot be made on the connection line cross-sectional shape and thickness (shown as Tr and Tc in the drawing) due to the difference in the density of the surrounding connection lines and the layout of the dummy lines 12 and 16 formed thereby. For the connecting wire, the resistor and the capacitor of the connecting wire are extracted under the same layout and thickness, but the premise of the connecting wire cannot be achieved in practice, so that the parameter cannot be extracted accurately. In the case of a design requiring accuracy in terms of layout parasitic parameter extraction (Layout Parasitic Extraction, LPE), the above-mentioned problems are particularly responsible for the degradation of the accuracy of circuit performance prediction because of direct correlation between the simulation results and the resistance or capacitance measurement errors due to the difference in thickness of the connection lines and the like. Disclosure of Invention The invention aims to provide a semiconductor device testing structure and a semiconductor device evaluation method using the same, and aims to realize accurate measurement of resistance and capacitance in a semiconductor device connecting wire structure by using the same testing structure. The invention provides a semiconductor device testing structure which is characterized by comprising a resistance measuring line, a capacitance measuring line and a dummy line, wherein the resistance measuring line and the capacitance measuring line are arranged on a semiconductor substrate in the same layer, the resistance measuring line is used for measuring the resistance of a connecting line, the capacitance measuring line is used for measuring the capacitance of the connecting line, the capacitance measuring line comprises a first capacitance measuring line and a second capacitance measuring line, the first capacitance measuring line and the second capacitance measuring line are respectively arranged on two sides of the resistance measuring line, and the dummy line is arranged on adjacent layers of the resistance measuring line and the capacitance measuring line. In some embodiments, the first and second capacitance measurement lines each comprise a plurality of comb-like connection lines such that the first and second capacitance measurement lines are each in a comb-like pattern. In some embodiments, the capacitance measuring line includes two first capacitance measuring lines and two second capacitance measuring lines, the two first capacitance measuring lines are inserted relatively, the two second capacitance measuring lines are inserted relatively, the two first capacitance measuring lines and the two second capacitance measuring lines are connected to four measuring ends, and the four measuring ends are used for four-endpoint resistance measurement. In some embodiments, the dummy lines include a first dummy line and/or a second dummy line, the first dummy line being provided in a lower layer of the resistance measurement line and the capacitance measurement line, and/or the second dummy line being provided in an upper layer of the resistance measurement line and the capacitance measurement line. In some embodiments, the first dummy line and/or the second dummy line may be grounded or a predetermined voltage is applied. In some embodiments, a third dummy line is further included, the third dummy line being disposed in an adjacent region outside the first and second capacitance measurement lines. On the other hand, the invention also provides a semiconductor device evaluation method, which uses the semiconductor device test structure and compri