CN-121541031-B - Chip failure analysis method and device

CN121541031BCN 121541031 BCN121541031 BCN 121541031BCN-121541031-B

Abstract

The disclosure provides a chip failure analysis method and device, which can solve the technical problem that the related technology cannot perform failure analysis on an advanced process. The method comprises the steps of obtaining an electrical measurement result through combined testing of body diodes of a plurality of metal oxide semiconductor MOS tubes and combined testing of the MOS tubes and the body diodes under the condition that a chip is delaminated to a contact layer, and obtaining a failure analysis result of the chip according to the electrical measurement result. Under the condition that the chip is delaminated to the contact layer (namely Via 0), whether Via 0 is abnormal or not is directly judged by utilizing the body diode effect of the MOS tube through electrical measurement. And quickly positioning at the Via 0 end by utilizing the body diode of the MOS tube, the combination of the body diode and the MOS tube to obtain a failure analysis result of the chip. At most three pins are needed for abnormal electrical testing, and the testing time is shortened by 50%. Furthermore, the carbon deposition on the surface of the sample is reduced, and the introduction of analysis noise is reduced.

Inventors

TONG TAO
LI WANLI
WANG HUILIN
WANG XIAOLIN

Assignees

深圳江原科技有限公司

Dates

Publication Date: 20260508
Application Date: 20260119

Claims (8)

1. A method for chip failure analysis, the method comprising: Under the condition that the chip is delaminated to the contact layer, an electrical measurement result is obtained through the combined test of the body diodes of the MOS tubes and the combined test of the MOS tubes and the body diodes; Obtaining a failure analysis result of the chip according to the electrical measurement result; Under the condition that a chip is delaminated to a contact layer, through the combined test of body diodes of a plurality of MOS (metal oxide semiconductor) tubes and the combined test of the MOS tubes and the body diodes, when the step of obtaining an electrical measurement result is carried out, the plurality of MOS tubes comprise a first MOS tube, a second MOS tube and a third MOS tube; The method comprises the following steps: Performing an electrical test on the contact layer to obtain an electrical measurement result of the contact layer; applying a voltage between a substrate end and a source electrode of the first MOS tube, and determining an electrical measurement result of the source electrode of the first MOS tube based on an electrical curve of a body diode of the first MOS tube; And fixing high voltage on the grid electrode of the first MOS tube, grounding the substrate of the third MOS tube, scanning the source electrode of the first MOS tube by using a step voltage, and determining an electrical measurement result of the grid electrode of the first MOS tube by testing electrical curves of the first MOS tube and a second body diode of the third MOS tube, wherein the second body diode is a PN junction formed between the drain electrode of the PU1 and the BUIK end.
2. The method of claim 1, wherein the chip comprises a memory structure comprising a plurality of bit cells, the method further comprising: determining the electrical measurement of each of the bit cells one by one; marking the contact layer of any one of the bit cells as an abnormal contact layer if the electrical measurement of the bit cell is invalid; and obtaining the failure analysis result based on destructive analysis according to the abnormal contact layer.
3. The method of claim 1, wherein the method comprises: Applying voltage between the substrate end and the source electrode of the second MOS tube, and determining an electrical measurement result of the source electrode of the second MOS tube based on an electrical curve of a body diode of the second MOS tube, wherein the first MOS tube and the second MOS tube share the same substrate end.
4. The method of claim 1, wherein the method comprises: And applying voltage between the substrate end and the source electrode of the third MOS tube, and determining an electrical measurement result of the source electrode of the third MOS tube based on an electrical curve of a first body diode of the third MOS tube, wherein the first body diode is a PN junction formed between the source electrode of the PU1 and the BUIK end.
5. The method of claim 2, wherein the memory structure is a static random access memory, and each bit cell comprises six MOS transistors.
6. The method of claim 2, wherein the contact layer is a layer in which Via0 is located.
7. The method of claim 1, wherein the method comprises: if the current and the voltage are linearly related in the electrical curve, the electrical measurement result is normal; if there is a high resistance anomaly in the electrical profile, the electrical measurement is anomaly.
8. A chip failure analysis apparatus, characterized in that the chip failure analysis apparatus is configured to perform the method of any one of claims 1 to 7.

Description

Chip failure analysis method and device Technical Field The disclosure relates to the technical field of chip failure analysis, in particular to a chip failure analysis method and device. Background Failure analysis of chips is an important means in the field of integrated circuits. Through failure analysis, the root cause of the chip failure can be positioned, the process yield is improved by assistance, and the chip design is optimized. With the evolution of integrated circuit process nodes, failure analysis techniques are advancing, and nano probes (nanoprobes) have become important tools for electrical property of advanced Cheng Zhongbiao-feature Metal Oxide Semiconductor (MOS) tubes and chip anomalies. Currently, there are three main existing methods for failure analysis in the mature process. Firstly, directly removing layers to a zero layer Metal (Metal 0), and testing the electrical property of a single Metal Oxide Semiconductor (MOS) tube at the zero layer Metal (Metal 0) end to assist in judging whether a contact layer (Via 0) is normal or not. And secondly, removing layers to the end of the contact layer (Via 0), and judging an abnormal link through two groups of combined tests of PG+PU and PG+PD. Thirdly, if design for testability (DFT) data is sufficiently clear, destructive analysis such as Transmission Electron Microscopy (TEM) is directly performed on the target region. However, in the advanced process, after the Static Random Access Memory (SRAM) is delaminated to the contact layer (Via 0), the Metal Oxide Semiconductor (MOS) transistors are not independent of each other, which results in incapacity of electrical measurement alone, and the abnormality of the contact layer (Via 0) itself is still a core problem in failure analysis. Disclosure of Invention The disclosure provides a chip failure analysis method and device, which can solve the technical problem that the related technology cannot perform failure analysis on an advanced process. In a first aspect, the disclosure provides a method for analyzing a chip failure, where the method includes obtaining an electrical measurement result through a combination test of body diodes of a plurality of Metal Oxide Semiconductor (MOS) transistors and a combination test of the MOS transistors and the body diodes under a condition that the chip is delaminated to a contact layer, and obtaining a failure analysis result of the chip according to the electrical measurement result. Based on the above description of the chip failure analysis method provided by the embodiment of the application, it can be known that, under the condition that the chip is delaminated to the contact layer (i.e. Via 0), whether Via 0 is abnormal is directly determined by using the body diode effect of the MOS transistor through electrical measurement. And rapidly positioning at the Via 0 end by utilizing the body diode of the MOS tube, the body diode and the MOS tube combination to obtain a failure analysis result of the chip so as to finish the operation of performing failure analysis on the prior process. And, at most three pins are needed for abnormal electrical test, and the test time is shortened by 50%. Furthermore, the carbon deposition on the surface of the sample can be effectively reduced, and the introduction of analysis noise is reduced. In one implementation manner of the first aspect, the chip includes a memory structure, the memory structure includes a plurality of bit units, the method further includes determining an electrical measurement result of each bit unit one by one, marking a contact layer of a bit unit as an abnormal contact layer if the electrical measurement result of any bit unit is invalid, and obtaining a failure analysis result based on destructive analysis according to the abnormal contact layer. And if the failure occurs in Via0, the abnormal Via0 can be directly locked for the next destructive analysis, so that analysis resources and time are saved. In one implementation manner of the first aspect, under the condition that a chip is delaminated to a contact layer, performing a combination test on body diodes of a plurality of Metal Oxide Semiconductor (MOS) transistors, and a combination test on the MOS transistors and the body diodes to obtain an electrical measurement result, wherein the MOS transistors comprise a first MOS transistor, a second MOS transistor and a third MOS transistor. In one implementation manner of the first aspect, the method includes fixing a high voltage on a gate of the first MOS transistor, grounding a substrate of the third MOS transistor, scanning a source of the first MOS transistor with a step voltage, and determining an electrical measurement result of the gate of the first MOS transistor by testing electrical curves of the first MOS transistor and a second body diode of the third MOS transistor. In one implementation manner of the first aspect, the method includes applying a voltage between a substrate end and