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CN-121541819-B - Cross-clock-domain JTAG system sampling control method and storage medium

CN121541819BCN 121541819 BCN121541819 BCN 121541819BCN-121541819-B

Abstract

The application discloses a sampling control method and a storage medium of a cross-clock-domain JTAG system, which relate to the technical field of CPU sampling control and disclose the sampling control method of the cross-clock-domain JTAG system, wherein the system comprises a main controller, a programmable logic device and JTAG target equipment, the main controller is electrically connected with the programmable logic device, the programmable logic device is electrically connected with the JTAG target equipment, the method comprises the steps of obtaining a clock signal of the main controller, collecting detection data of the JTAG target equipment according to a preset sampling condition according to the clock signal, analyzing the detection data and checking through a preset checking model to generate transaction data and uploading the transaction data to the main controller, and thus, the accurate sampling control of the JTAG target equipment in a cross-clock-domain environment is realized. The method effectively solves the problem of sampling errors possibly caused by different clock domains, and improves the accuracy and reliability of data acquisition.

Inventors

  • LI XIAOFENG

Assignees

  • 四川华鲲振宇智能科技有限责任公司

Dates

Publication Date
20260508
Application Date
20260120

Claims (8)

  1. 1. A sampling control method of a cross-clock domain JTAG system is characterized in that the system comprises a main controller, a programmable logic device and JTAG target equipment, wherein the main controller is electrically connected with the programmable logic device, and the programmable logic device is electrically connected with the JTAG target equipment, and the method comprises the following steps: Acquiring a clock signal of the main controller; Acquiring detection data of the JTAG target equipment according to the clock signal and a preset sampling condition; Analyzing the detection data and checking through a preset checking model to generate transaction data and uploading the transaction data to the main controller; the programmable logic device comprises a clock monitoring and calculating module, and the step of acquiring the clock signal of the main controller is set as follows: The clock monitoring and calculating module monitors and calculates the frequency drift rate and the clock fluctuation rate of the main controller in real time; the programmable logic device further comprises an asynchronous FIFO module and a TDO sampling module, and the step of collecting the detection data of the JTAG target device according to the clock signal and the preset sampling condition comprises the following steps: when the frequency drift rate exceeds a first threshold value, the Gray code synchronous beat number of the asynchronous FIFO module is increased, and the near-full threshold value of the asynchronous FIFO module is reduced; and/or when the clock fluctuation rate exceeds a second threshold, the TDO sampling module switches to a high-speed sampling mode to collect the detection data.
  2. 2. The method of claim 1, wherein the programmable logic device comprises a transaction verification module, and wherein the step of parsing the test data and verifying by a preset verification model comprises: the programmable logic device samples detection data returned by the JTAG target equipment; And analyzing and comparing according to the instruction code set or the predefined constraint of the detection data to judge the abnormal state data of the detection data.
  3. 3. The method of clock domain-crossing JTAG system sampling control of claim 2, wherein said programmable logic device comprises a TBM generation module, said step of generating transaction data to upload to said host controller comprising: The TBM generation module acquires the detection data and the abnormal state data; And generating a data packet of the transaction data according to a preset rule for the detection data and the abnormal state, and uploading the data packet to the main controller.
  4. 4. The method of claim 3, wherein the predetermined rule is set to the TBM generation module generating the transaction data according to a fixed bit sequence, a working transaction ID of the JTAG target device, a channel ID of the JTAG target device, a data length of the transaction data, a transaction type of the JTAG target device, an exception status flag, a transaction priority field, and a CRC check field.
  5. 5. The method for controlling sampling of a cross-clock domain JTAG system according to claim 1, wherein after the step of parsing the detection data and checking by a preset check model to generate transaction data, the step of uploading the transaction data to the host controller further comprises: And the master controller performs matching verification according to the received transaction data so as to output a first transaction abnormal signal or a second transaction abnormal signal to the programmable logic device when the transaction data is abnormal.
  6. 6. The method of claim 5, wherein the step of the master controller performing a match check based on the received transaction data to output a first transaction exception signal or a second transaction exception signal to the programmable logic device when the transaction data is abnormal further comprises: the programmable logic device discards current transaction data and re-collects detection data of the JTAG target device according to the received first transaction abnormal signal; Or the programmable logic device pauses the current data transmission task according to the second transaction abnormal signal.
  7. 7. The method of claim 1, wherein the step of the clock monitoring and calculating module monitoring and calculating the frequency drift rate and the clock fluctuation rate of the main controller in real time comprises obtaining the clock fluctuation rate of the main controller according to the following formula: Wherein T i represents the number of local clock cycles corresponding to the ith TCK period, T1 is the average number in the continuous ith TCK period, N is the sliding sampling window length, and default n=64.
  8. 8. A storage medium, characterized in that the storage medium is a computer readable storage medium, on which a computer program is stored, which computer program, when being executed by a processor, implements the steps of the clock domain crossing JTAG system sampling control method according to any one of claims 1 to 7.

Description

Cross-clock-domain JTAG system sampling control method and storage medium Technical Field The application relates to the technical field of CPU sampling control, in particular to a clock domain-crossing JTAG system sampling control method and a storage medium. Background In the field of embedded systems and chip level debugging, a JTAG interface is widely applied to register access, boundary scan test and fault diagnosis operation of target equipment as a core debugging mechanism of IEEE 1149.1 standard. However, when the main controller and the JTAG target device are in asynchronous clock domain operation, the TCK clock signal is inevitably interfered by frequency drift and clock jitter, resulting in offset of TDO data sampling points, causing serious problems such as sampling misalignment, transaction boundary identification confusion, and key data packet loss. The traditional solutions generally adopt a synchronous FIFO structure with fixed parameters and a static sampling strategy, and the methods lack flexibility under a dynamic clock environment and cannot carry out self-adaptive adjustment according to real-time clock fluctuation, so that the buffer mechanism is low in efficiency. Meanwhile, the existing system does not integrate a real-time check function of transaction behaviors, so that protocol illegal operation or abnormal response data are difficult to effectively detect, and error information is mistransmitted to the main controller. More prominently, after detecting transmission anomalies, the system generally relies on coarse-grained restoration means such as global reset, which not only forces the current debug task to be interrupted, but also significantly reduces the continuity and overall availability of the debug link. Therefore, there is a need to develop a clock domain-crossing JTAG sampling control mechanism capable of sensing clock state changes in real time, dynamically optimizing sampling and buffering policies, and implementing hierarchical exception handling based on structured transaction metadata to improve the robustness, security, and real-time response capabilities of the debugging process. Disclosure of Invention The application mainly aims to provide a cross-clock domain JTAG system sampling control method and a storage medium, and aims to solve the technical problems of improving accuracy and reliability of cross-clock domain data sampling, enhancing system robustness and reducing debugging task interruption. In order to achieve the above objective, the present application provides a method for controlling sampling of a clock domain-crossing JTAG system, the system comprises a main controller, a programmable logic device and a JTAG target device, wherein the main controller is electrically connected with the programmable logic device, the programmable logic device is electrically connected with the JTAG target device, the method comprises: Acquiring a clock signal of the main controller; Acquiring detection data of the JTAG target equipment according to the clock signal and a preset sampling condition; Analyzing the detection data and checking through a preset checking model to generate transaction data and uploading the transaction data to the main controller. In one embodiment, the programmable logic device includes a clock monitoring and calculating module, and the step of obtaining the clock signal of the main controller is configured to: the clock monitoring and calculating module monitors and calculates the frequency drift rate and the clock fluctuation rate of the main controller in real time. In an embodiment, the programmable logic device further includes an asynchronous FIFO module and a TDO sampling module, and the step of collecting the detection data of the JTAG target device according to the clock signal and the preset condition includes: when the frequency drift rate exceeds a first threshold value, the Gray code synchronous beat number of the asynchronous FIFO module is increased, and the near-full threshold value of the asynchronous FIFO module is reduced; and/or when the clock fluctuation rate exceeds a second threshold, the TDO sampling module switches to a high-speed sampling mode to collect the detection data. In one embodiment, the programmable logic device includes a transaction verification module, and the step of parsing the detection data and verifying by a preset verification model includes: the programmable logic device samples detection data returned by the JTAG target equipment; And analyzing and comparing according to the instruction code set or the predefined constraint of the detection data so as to judge the abnormal state of the detection data. In one embodiment, the programmable logic device includes a TBM generation module, and the step of generating transaction data for uploading to the host controller includes: the TBM generation module acquires the detection data and the abnormal state thereof; And generating a data packet of the t