CN-121542211-B - FPGA platform multi-chip interconnection verification system and verification method

CN121542211BCN 121542211 BCN121542211 BCN 121542211BCN-121542211-B

Abstract

The application provides an FPGA platform multi-chip interconnection verification system and an FPGA platform multi-chip interconnection verification method, wherein the verification system comprises a plurality of programmable logic devices, each programmable logic device is in communication connection with at least one programmable logic device, a simulation logic module for simulating the function of a target chip is configured on each programmable logic device, the verification system further comprises a host, a plurality of programmable logic devices and a controller, wherein the host is in communication connection with the plurality of programmable logic devices and is configured to perform data transmission with the plurality of programmable logic devices at a medium access control layer of Ethernet through an Ethernet communication interface; and each inter-chip interconnection module is in communication connection with the Ethernet communication interface in the corresponding programmable logic device, and the inter-chip interconnection module is configured to perform data transmission with at least one programmable logic device through the Ethernet communication interface and the serial-parallel receiving-transmitting unit of the programmable logic device where the inter-chip interconnection module is positioned.

Inventors

KE YALIN

Assignees

格通智联技术(上海)有限公司

Dates

Publication Date: 20260508
Application Date: 20260119

Claims (3)

1. An FPGA platform multi-chip interconnection verification system, including a plurality of programmable logic devices, each of the programmable logic devices is communicatively connected to at least one of the programmable logic devices, and each of the programmable logic devices is configured with a simulation logic module for simulating a function of a target chip, the FPGA platform multi-chip interconnection verification system further includes: The host is in communication connection with the plurality of programmable logic devices and is configured to perform data transmission between a medium access control layer of the Ethernet and the plurality of programmable logic devices in an original socket communication mode through an Ethernet communication interface so as to construct and analyze a custom Ethernet frame or a custom network layer message loaded on the Ethernet at the medium access control layer of the Ethernet, wherein the Ethernet frame comprises a type field for indicating a verification item and/or a verifier corresponding to the Ethernet frame, and the custom network layer message comprises a type field for indicating the verification item and/or the verifier corresponding to the custom network layer message; And each inter-chip interconnection module is in communication connection with the Ethernet communication interface of the corresponding programmable logic device, wherein the inter-chip interconnection module is configured to perform data transmission with at least one programmable logic device through the Ethernet communication interface and the serial-parallel receiving-transmitting unit of the programmable logic device where the inter-chip interconnection module is located.
2. The FPGA platform multi-chip interconnect verification system of claim 1, wherein each of the inter-chip interconnect modules comprises a data encapsulation module, a data scheduling module, a first data caching module, and a data combining module, and a data splitting module, a second data caching module, and a data grouping module, all of which are in communication connection in sequence.
3. The method for verifying the interconnection of multiple chips of an FPGA platform is used for verifying the functions of a target chip based on a plurality of simulation logic modules, wherein the simulation logic modules are respectively configured on corresponding programmable logic devices, and each programmable logic device is in communication connection with at least one programmable logic device, and the method is characterized by comprising the following steps: Data transmission is carried out between a medium access control layer of an Ethernet and the plurality of programmable logic devices in an original socket communication mode through an Ethernet communication interface so as to construct and analyze a custom Ethernet frame or a custom network layer message loaded on the Ethernet at the medium access control layer of the Ethernet, wherein the Ethernet frame comprises a type field for indicating a verification item and/or a verifier corresponding to the Ethernet frame, the custom network layer message comprises a type field for indicating the verification item and/or the verifier corresponding to the custom network layer message, and The control inter-chip interconnection module performs data transmission with at least one programmable logic device through an Ethernet communication interface and a serial-parallel receiving unit of the programmable logic device where the control inter-chip interconnection module is located, wherein the inter-chip interconnection module is in communication connection with the Ethernet communication interface in the programmable logic device where the control inter-chip interconnection module is located.

Description

FPGA platform multi-chip interconnection verification system and verification method Technical Field The application mainly relates to the field of chip verification, in particular to an FPGA platform multi-chip interconnection verification system and an FPGA platform multi-chip interconnection verification method. Background Functional verification of chips before mass production is a key link for ensuring the reliability of products, and GPU (graphics processing unit) is an important chip type, and is particularly important for verification. In recent years, with the rapid development of artificial intelligence, particularly large models, it has been difficult for a single GPU to meet the ever-increasing computational power demands, and thus higher computational power needs to be provided through the interconnection cooperation of multiple GPUs. In order to support interconnection scenes of different scales and topological forms, various types of high-speed interconnection interfaces and protocols are introduced into chips by all GPU manufacturers. Before mass production, the running condition of the GPU under different networking models needs to be verified under the condition of multi-card interconnection so as to ensure the functional correctness and running stability of the GPU under the complex networking condition. In consideration of efficiency, cost and other factors, a verification platform based on a programmable logic device is generally selected for verification. When an FPGA is adopted to build a complex networking model, a plurality of technical difficulties are faced, namely, on one hand, the networking scale is larger, the number of the related chips is large, fine access isolation and unified control management between different chips are required to be realized, and on the other hand, the interconnection interface protocols of different GPU manufacturers are inconsistent, and protocol adaptation and connection mapping are required to be carried out on an FPGA platform. Disclosure of Invention The technical problem to be solved by the application is to provide an FPGA platform multi-chip interconnection verification system and an FPGA platform multi-chip interconnection verification method, which have the effects of low verification difficulty and low verification cost. The application provides an FPGA platform multi-chip interconnection verification system, which comprises a plurality of programmable logic devices, a host and a plurality of inter-chip interconnection modules, wherein each programmable logic device is in communication connection with at least one programmable logic device, each programmable logic device is provided with a simulation logic module for simulating the function of a target chip, the simulation logic module is in communication connection with the plurality of programmable logic devices, the host is configured to perform data transmission with the plurality of programmable logic devices through an Ethernet communication interface at a medium access control layer of Ethernet, each inter-chip interconnection module is in communication connection with the Ethernet communication interface of the corresponding programmable logic device, and the inter-chip interconnection modules are configured to perform data transmission with at least one programmable logic device through the Ethernet communication interface and a serial-parallel transceiving unit of the programmable logic device where the inter-chip interconnection modules are located. The application further provides a multi-chip interconnection verification method of the FPGA platform, which is used for verifying functions of a target chip based on a plurality of simulation logic modules, wherein the simulation logic modules are respectively configured on corresponding programmable logic devices, each programmable logic device is in communication connection with at least one programmable logic device, the method comprises the steps of carrying out data transmission on a medium access control layer of Ethernet and the programmable logic devices through an Ethernet communication interface, and controlling an inter-chip interconnection module to carry out data transmission on the inter-chip interconnection module and the at least one programmable logic device through the Ethernet communication interface and a serial-parallel receiving unit of the programmable logic device where the inter-chip interconnection module is located, wherein the inter-chip interconnection module is in communication connection with the Ethernet communication interface in the programmable logic device where the inter-chip interconnection module is located. The technical scheme of the application has the technical effects that the programmable logic device is limited by factors such as production cost, manufacturer operation strategy, device resources and the like, and the programmable logic device usually does not have a complete network pro