CN-121548103-B - GaN HEMT monolithic integrated complementary type inverter and device manufacturing method thereof

CN121548103BCN 121548103 BCN121548103 BCN 121548103BCN-121548103-B

Abstract

The invention discloses a GaN HEMT monolithic integrated complementary inverter and a device preparation method thereof, and relates to the technical field of semiconductors, wherein the inverter comprises an n-channel enhanced GaN HEMT and a P-channel enhanced GaN HEMT which are transversely distributed on a common epitaxial layer of the same substrate; the two-dimensional dielectric layer, the graphene layer and the isolation dielectric layer are sequentially arranged above the epitaxial layer, the source and drain electrodes of the P-channel device are arranged in grooves after the isolation dielectric layer and the graphene layer are etched, the grooves of the grid electrode are etched into the P-GaN layer, the source and drain electrodes of the n-channel device are arranged in grooves from the epitaxial layer to the bottom of the barrier layer, the grid electrode is arranged above the unetched P-GaN layer, and isolation is achieved among the devices through isolation grooves penetrating into the buffer layer. According to the invention, by introducing the two-dimensional dielectric layer and the graphene layer, two-dimensional hole gas is induced at the P-GaN interface, so that the hole carrier concentration is remarkably improved, the performance bottleneck of a P-channel device is solved, and the monolithic integrated complementary logic with high speed and low power consumption is realized.

Inventors

ZHANG JING
MA SHENGHENG
WANG LIANSHAN
CHEN FUXIN
ZHAO BAIYU

Assignees

中科(深圳)无线半导体有限公司

Dates

Publication Date: 20260505
Application Date: 20260120

Claims (10)

1. The GaN HEMT monolithic integrated complementary type inverter is characterized by comprising an n-channel enhanced GaN HEMT and a p-channel enhanced GaN HEMT, wherein the n-channel enhanced GaN HEMT and the p-channel enhanced GaN HEMT are prepared on the same substrate and distributed along the transverse direction of the substrate; an epitaxial layer shared by the n-channel enhanced GaN HEMT and the P-channel enhanced GaN HEMT is arranged above one side of the substrate, and the epitaxial layer sequentially comprises a nucleation layer, a buffer layer, a channel layer, a barrier layer and a P-GaN layer from bottom to top; Source electrode ohmic metal and drain electrode ohmic metal of the p-channel enhanced GaN HEMT are arranged in a groove formed after the isolation dielectric layer and the graphene layer are partially etched; a grid groove etched into the P-GaN layer is formed between the source electrode and the drain electrode of the P-channel enhanced GaN HEMT, a compact dielectric layer is arranged in the grid groove, and a P-channel grid electrode is arranged above the compact dielectric layer; The source electrode ohmic metal and the drain electrode ohmic metal of the n-channel enhanced GaN HEMT are arranged in a groove formed from the epitaxial layer to the bottom of the barrier layer through etching; the method comprises the steps of forming a P-GaN layer region on a substrate, etching a graphene layer of the n-channel enhanced GaN HEMT in the n-channel enhanced GaN HEMT, removing the P-GaN layer outside the n-channel enhanced GaN HEMT by selective etching, wherein the P-GaN layer is not etched above the P-GaN layer region between a source electrode and a drain electrode of the n-channel enhanced GaN HEMT, and an n-channel gate electrode is arranged above the dense dielectric layer; The wafer area provided with the isolation groove is a passive area, the wafer area provided with the n-channel enhanced GaN HEMT and the p-channel enhanced GaN HEMT is an active area, and the passive area surrounds the active area to form electric isolation between devices in an epitaxial layer.
2. The GaN HEMT monolithic integrated complementary type inverter according to claim 1 is characterized in that the nucleation layer is made of AlN material, the buffer layer is made of high-resistance GaN material, the channel layer is made of unintentionally doped intrinsic GaN material, the barrier layer is made of AlxGa (1-x) N material with gradually reduced Al component, wherein x is more than or equal to 0.25 and less than or equal to 0.75, the P-GaN layer is made of Mg ion doped P-type GaN material, the two-dimensional medium layer is made of hexagonal boron nitride h-BN material with the thickness range of 2-5 nm, the graphene layer is of a single-layer or multi-layer structure, the isolation medium layer is made of AlN material, and the thickness range of 2-10 nm.
3. The GaN HEMT monolithically integrated complementary inverter of claim 1, wherein the source and drain ohmic metals of the p-channel enhancement GaN HEMT are stacked with one or more of Ni, pt, pd metals, and the source and drain ohmic metals of the n-channel enhancement GaN HEMT are stacked with one or more of Ti, al, ni, pt, pd, W metals.
4. The GaN HEMT monolithically integrated complementary inverter according to claim 1, wherein the dense dielectric layer is made of Al 2 O 3 or HfO 2 , and the p-channel gate electrode and the n-channel gate electrode are stacked by one or more of Ni, pt, pd, W metals.
5. The GaN HEMT monolithic integrated complementary inverter according to claim 1 is characterized in that passivation layers made of SiO 2 or Si 3 N 4 materials are further arranged above the active area and the passive area, metal electrodes are exposed through etching the passivation layers above electrodes of the n-channel enhanced GaN HEMT and the p-channel enhanced GaN HEMT, a metal interconnection layer is obtained through a metal deposition process, the metal interconnection layer is made of Al or Cu metal, and electrical connection among devices is formed through leading out the metal electrodes according to a circuit connection sequence.
6. The GaN HEMT monolithically integrated complementary inverter according to claim 1, wherein a source of the p-channel enhancement type GaN HEMT is connected to a power supply voltage VDD, a gate electrode of the p-channel enhancement type GaN HEMT is connected to a gate electrode of the n-channel enhancement type GaN HEMT and serves as an input voltage VIN terminal, a drain of the p-channel enhancement type GaN HEMT is connected to a drain of the n-channel enhancement type GaN HEMT and serves as an output voltage VOUT terminal, and a source of the n-channel enhancement type GaN HEMT is connected to a ground electrode GND.
7. A method of fabricating a GaN HEMT monolithically integrated complementary inverter device of any one of claims 1-6, comprising: Providing a substrate, and sequentially growing a nucleation layer, a buffer layer, a channel layer, a barrier layer and a P-GaN layer on the substrate to complete epitaxial layer growth; selecting a substrate, and growing a graphene layer and a two-dimensional medium layer on the substrate; Turning over the substrate on which the graphene layer and the two-dimensional dielectric layer are grown, bonding the two-dimensional dielectric layer and the P-GaN layer of the epitaxial layer, and stripping the substrate, so that the graphene layer and the two-dimensional dielectric layer are transferred to the upper part of the P-GaN layer; Growing an isolation medium layer above the graphene layer; Selectively etching the isolation dielectric layer and the graphene layer, and depositing source electrode metal and drain electrode metal of the p-channel enhanced GaN HEMT in the etched groove; Selectively etching the epitaxial layer to the buffer layer to form an isolation groove, etching the P-GaN layer and part of the barrier layer of the n-channel enhanced GaN HEMT region, and depositing source electrode and drain electrode metals of the n-channel enhanced GaN HEMT; Selectively etching an epitaxial layer of a P-channel enhanced GaN HEMT gate region into the P-GaN layer to form a gate groove; Depositing a dense dielectric layer on one side of the epitaxial layer far away from the substrate, and preparing a metal gate in a gate groove of the P-channel enhanced GaN HEMT and above the unetched P-GaN layer of the n-channel enhanced GaN HEMT; and depositing a passivation layer, etching the contact hole and depositing an interconnection metal layer to finish the preparation of the device.
8. The method of fabricating a device according to claim 7, wherein the method of flipping and bonding the substrate on which the graphene layer and the two-dimensional dielectric layer are grown comprises placing the substrate in a bonder, aligning and bonding the two-dimensional dielectric layer with the P-GaN layer, separating the substrate from the graphene layer by chemical etching or laser lift-off, and optimizing a bonding interface by low temperature annealing.
9. The device manufacturing method according to claim 7, wherein before the isolation medium layer is grown, oxygen plasma treatment is performed on the epitaxial wafer to activate the surface of the graphene layer, and the growth of the isolation medium layer comprises transferring the epitaxial wafer into an atomic layer deposition device to grow an AlN material as the isolation medium layer.
10. The device manufacturing method according to claim 7, wherein ohmic contact is achieved through low-temperature rapid annealing after source and drain metals of the p-channel enhancement type GaN HEMT are deposited and after source and drain metals of the n-channel enhancement type GaN HEMT are deposited, the dense dielectric layer is manufactured through an atomic layer deposition process, and the passivation layer is subjected to surface planarization through a chemical mechanical polishing process.

Description

GaN HEMT monolithic integrated complementary type inverter and device manufacturing method thereof Technical Field The invention relates to the technical field of semiconductors, in particular to a GaN HEMT monolithic integrated complementary type inverter and a device manufacturing method thereof. Background GaN (gallium nitride) is used as a wide-bandgap (3.4 eV) semiconductor material, has extremely high critical electric field (about 3 MV/cm) and excellent thermal conductivity (about 130W/m.K), and a GaN-based High Electron Mobility Transistor (HEMT) forms two-dimensional electron gas (2 DEG) by utilizing the strong polarization effect of AlGaN/GaN heterojunction, and has high electron mobility (up to 1500cm 2/V.s), so that the HEMT device can realize low on-resistance, fast switching and reliable power conversion under high-voltage, high-frequency and high-temperature environments, and has been widely used in radio frequency power amplifiers, DC-DC converters and power management chips. However, the current driving circuit of the GaN HEMT switching tube is generally based on a Si-based MOSFET device, and the disadvantages of slow response speed, large chip area and the like are contrary to the advantages of the GaN HEMT device. Accordingly, researchers have attempted to build transistors with GaN HEMT devices as driving circuits, so GaN HEMT-based inverters have received attention as the basic structure of driving circuits. The complementary type phase inverter (CMOS-STYLE INVERTER) maintains the zero static power consumption characteristic of the CMOS, has the advantages of high breakdown voltage and high-speed switch of GaN, can realize the rising/falling time of wide working voltage (5V-200V) and subnanosecond level, and is particularly suitable for digital control of a power module, a bias circuit of a radio frequency front end and the like. However, the too low hole carrier concentration of the p-channel enhancement type GaN HEMT is always a bottleneck for restricting the performance of the complementary device, so that the on-resistance (Ron) of the p-channel device is far higher than that of the n-channel device, the pull-up current is insufficient, and further the problems of slow rising edge, reduced noise margin, insufficient saturation of the output high level and the like occur. In order to raise the hole concentration of P-GaN, various schemes have been proposed in the academy, such as raising the polarization electric field by introducing an AlGaN barrier layer with high Al content, further enhancing hole injection, and raising the hole concentration by activating holes after hydrogen passivation of a Mg-doped GaN layer. Although the above method has been developed in the laboratory, the common problems of large lattice mismatch of the insertion layer, low carrier concentration, unstable threshold value, insufficient high-temperature reliability and the like are faced, so that the pull-up current matched with the n-channel GaN HEMT is difficult to realize in the actual power cascade chip. Therefore, other methods are needed to increase the hole concentration of the P-GaN layer, thereby realizing a truly symmetrical GaN complementary inverter with low power consumption. Because the p-type two-dimensional material graphene has a proper work function relative to GaN, and because of different energy band structures of the two materials, charge transfer can occur at a contact interface, so that a hole accumulation layer (namely 2 DHG) is induced on the surface of nitride. However, the interface quality of the graphene is poor due to the fact that the carbon lattice of the graphene is not matched with the lattice of the GaN, so that improvement of the interface quality of the graphene and the GaN is of practical significance for application of the graphene two-dimensional material in a complementary GaN inverter. Disclosure of Invention The invention provides a GaN HEMT monolithic integrated complementary type inverter and a device manufacturing method thereof, which can solve the problems. In order to solve the problems, the technical scheme adopted by the invention is as follows: the invention provides a GaN HEMT monolithically integrated complementary inverter, which comprises an n-channel enhanced GaN HEMT and a p-channel enhanced GaN HEMT, wherein the n-channel enhanced GaN HEMT and the p-channel enhanced GaN HEMT are prepared on the same substrate and distributed along the transverse direction of the substrate; an epitaxial layer shared by the n-channel enhanced GaN HEMT and the P-channel enhanced GaN HEMT is arranged above one side of the substrate, and the epitaxial layer sequentially comprises a nucleation layer, a buffer layer, a channel layer, a barrier layer and a P-GaN layer from bottom to top; Source electrode ohmic metal and drain electrode ohmic metal of the p-channel enhanced GaN HEMT are arranged in a groove formed after the isolation dielectric layer and the graphene layer ar