CN-121560789-B - SPI slave controller and chip

CN121560789BCN 121560789 BCN121560789 BCN 121560789BCN-121560789-B

Abstract

The invention discloses an SPI slave controller and a chip, and belongs to the technical field of integrated circuits. The SPI slave controller comprises an SPI interface, a core control module, a register module, an AHB system bus decoding module, a receiving buffer zone, a sending buffer zone, a receiving shift register and a sending shift register. The register module stores a control flag bit and a status flag bit. And the core control module works according to the control zone bit and detects the chip selection signal of the SPI interface in real time. And when the chip selection signal is invalid, setting a data transmission completion flag bit, and latching the final effective data length to a register module. The invention realizes the self-adaptive detection of the end transmission and the automatic recording of the effective data length of hardware without software pre-configuration or intervention of SPI transmission, and ensures the atomicity and the accuracy of data transmission.

Inventors

ZHANG WENJING
LANG XIAOGUANG
ZHANG JIANLONG
WANG XINLONG

Assignees

北京宏思电子技术有限责任公司

Dates

Publication Date: 20260512
Application Date: 20260121

Claims (7)

1. The SPI slave controller comprises an SPI interface, a transmission shift register, a transmission buffer zone, a reception shift register and a reception buffer zone, and is characterized in that the SPI slave controller is integrated on a chip, and the SPI slave controller further comprises a core control module, an AHB system bus decoding module and a register module; The register module is respectively connected with the sending buffer area, the receiving buffer area, the core control module and the AHB system bus decoding module, and is used for storing data from the receiving buffer area, the core control module and the AHB system bus decoding module, and also used for storing control zone bits and status zone bits, wherein the control zone bits at least comprise direction identification bits for identifying the data transmission direction, and the status zone bits at least comprise data transmission completion zone bits for identifying whether transmission is completed or not; The AHB system bus decoding module is respectively connected with the core control module and the register module and is used for responding to the request of the chip CPU and executing reading or writing operation on the register module; The core control module is respectively connected with the SPI interface, the sending buffer area, the receiving buffer area, the register module and the AHB system bus decoding module, and is used for determining and calculating the length of sending effective data or the length of receiving effective data according to the direction identification bit in the control zone bit stored in the register module, detecting the level state of a chip selection signal output by the SPI interface in real time, acquiring the data quantity in the sending buffer area or the receiving buffer area in real time when the chip selection signal is detected to be low level, calculating the length of sending or receiving effective data and storing the length of sending or receiving effective data into the register module, setting the data transmission completion zone bit in the register module when the chip selection signal is detected to be high level, and resetting the data transmission completion zone bit in the register module according to the control signal output by the AHB system bus decoding module; the core control module comprises a detection unit and a calculation unit; The detection unit is connected with the SPI interface, the register module and the AHB system bus decoding module, and is used for detecting a chip selection signal output by the SPI interface, setting the data transmission completion zone bit stored in the state register in the register module when the chip selection signal is detected to be at a high level, and resetting the data transmission completion zone bit stored in the state register in the register module according to a control signal output by the AHB system bus decoding module; The calculating unit is connected with the sending buffer area, the receiving buffer area and the register module and is used for acquiring the data storage quantity in the sending buffer area or the receiving buffer area in real time during the period that the chip selection signal is in a low level, acquiring the data writing or reading quantity of software to a data register in the register module, calculating the effective data length of sending or receiving, and storing the calculated effective data length into an effective length register in the register module.
2. The SPI slave controller of claim 1, wherein the register module comprises a data register, an effective length register, a status register, and a control register; The data register is connected with the sending buffer zone, the receiving buffer zone and the AHB system bus decoding module and is used for storing data to be sent or received data; The effective length register is connected with the core control module and the AHB system bus decoding module and is used for storing the effective data length calculated by the core control module; the status register is connected with the core control module and used for storing the data transmission completion zone bit; the control register is connected with the core control module and the AHB system bus decoding module and is used for storing a mode identification bit for configuring a data transmission mode and the direction identification bit.
3. The SPI slave controller according to claim 2, wherein the data register includes a transmit data register and a receive data register; the sending data register is respectively connected with the sending buffer zone, the AHB system bus decoding module and the effective length register and is used for storing data to be sent to a host; the receiving data register is respectively connected with the receiving buffer zone, the AHB system bus decoding module and the effective length register and is used for storing data received from a host.
4. The SPI slave controller according to claim 1, wherein the detection unit comprises a first trigger, a second trigger, a third trigger, a fourth trigger, a first and gate, a second and gate; The input end of the first trigger is connected with the chip selection signal output end of the SPI interface, the signals output by the SPI interface are subjected to primary synchronization, and the output end of the first trigger is connected with the input end of the second trigger; The second trigger resynchronizes the signal output by the first trigger, and the output end is respectively connected with the input end of the third trigger and the first input end of the first AND gate; the third trigger processes the signal output by the second trigger to obtain an inverted level signal, and the output end of the third trigger is connected with the second input end of the first AND gate; the first AND gate carries out AND operation on the signal output by the second trigger and the signal output by the third trigger to obtain a pulse signal, an output end is connected with a setting end of the fourth trigger, and the pulse signal obtained by operation is output to the setting end of the fourth trigger; The input end of the second AND gate is used for receiving the control signal output by the AHB system bus decoding module, performing AND operation on the control signal, and the output end of the second AND gate is connected with the reset end of the fourth trigger; The input end of the fourth trigger comprises a setting end and a resetting end, when a signal input by the setting end of the fourth trigger is a first pulse signal, the setting end of the fourth trigger is effective, the fourth trigger outputs a first preset value for setting the data transmission completion flag bit to a state register in the register module, and when a signal input by the resetting end of the fourth trigger is a second preset value, the resetting end of the fourth trigger is effective, and the fourth trigger outputs a third preset value for resetting the data transmission completion flag bit to the state register in the register module.
5. The SPI slave controller according to claim 1, wherein the computing unit comprises a first not gate, a second not gate, a third not gate, a counter, a first selector, a second selector, a first adder, a second adder, and a third adder; The first selector is configured to determine a current data direction under control of the direction identification bit in the register module, and select, according to the current data direction, a data register read enable signal or a write enable signal output by the AHB system bus decoding module to output the data register read enable signal or the write enable signal to the counter as a count enable signal; the counter is configured to count the total amount of data read or write in the data register by the AHB system bus decoding module during a high level of a count enable signal output by the first selector, and output a count value to the first adder; The first NOT gate is used for performing inverse operation on the read pointer value of the receiving buffer area and outputting an inverse operation result to the second adder; The second adder is configured to perform an addition operation on the negation operation result output by the first not gate and the write pointer value of the receiving buffer, obtain a data remaining amount of the receiving buffer, and output the data remaining amount of the receiving buffer to the second selector; The second NOT gate is used for performing inverse operation on the read pointer value of the sending buffer area and outputting an inverse operation result to the third adder; the third adder is configured to perform an addition operation on the negation operation result output by the second not gate and the write pointer value of the sending buffer, obtain a data remaining amount of the sending buffer, and output the data remaining amount of the sending buffer to the third not gate; the third NOT gate performs inverse operation on the data residual output by the third adder and outputs the data residual to the second selector; the second selector is used for selecting and outputting the result output by the second adder or the third NOT gate to the first adder according to the current data direction under the control of the direction identification bit; the first adder is configured to perform an addition operation according to the count value of the counter and the output value of the second selector to obtain an effective length of data that is sent or received, and output the effective length of data to an effective length register of the register module.
6. The SPI slave controller according to claim 1, wherein the AHB system bus decoding module is specifically configured to read data from a data register, an effective length register or a status register of the register module in response to a read request of a chip CPU, and return the data to the chip CPU through a bus; responding to a writing request of the chip CPU, and writing data on a bus into a control register or a data register of the register module; And responding to the writing operation of the chip CPU to the state register, and outputting a control signal for clearing the state flag bit to the core control module.
7. A chip comprising the SPI slave controller of any one of claims 1 to 6, said chip communicating with a host through said SPI slave controller.

Description

SPI slave controller and chip Technical Field The invention relates to an SPI slave controller and a chip, and belongs to the technical field of integrated circuits. Background With the rapid development of the information technology industry, a system on a chip (SoC) is used as a core chip for integrating a key computing core, a memory unit and rich peripheral interfaces, and its autonomous development and innovation capability are of great importance. Among the many peripheral interfaces of SoC chips, serial Peripheral Interface (SPI) is one of the most commonly used and critical interface standards for connecting peripheral devices such as flash memory, sensors, display modules, and communication modules, and plays an indispensable role in modern electronic systems, because of its advantages such as simple protocol, full duplex communication, and high speed. However, the SPI protocol itself mainly defines the timing relationship between clocks (SCK), data (MOSI, MISO) and chip select (SS) of the physical layer and the link layer, and does not specify a unified application layer data frame format or communication protocol. The feature gives the application developer great flexibility, can customize the communication message format according to the characteristics of specific peripheral equipment, but also brings significant challenges to the generalized and intelligent design of SPI Slave (Slave) hardware. Currently, when implementing a generic SPI slave controller in an SoC, start-stop control of data transmission of the generic SPI slave controller generally depends on deep intervention and preset of software (driver). The scheme adopted in the prior art has obvious limitations, and cannot be well adapted to flexible and changeable modern SPI application protocols, for example, a fixed-length transmission mode cannot be used for an application scene with variable data frame length and complex frame structure (for example, a protocol comprising a variable-length data field, a special frame tail separator or a requirement of dynamically determining the subsequent data length according to an intra-frame instruction field). Therefore, in the current SoC pursuing high performance, high integration and high reliability, there is a need for an SPI slave controller to solve the above problems. Disclosure of Invention In order to solve the technical problems, the invention provides an SPI slave controller and a chip. According to the first aspect of the invention, the SPI slave controller comprises an SPI interface, a transmission shift register, a transmission buffer zone, a reception shift register and a reception buffer zone, wherein the SPI slave controller is integrated on a chip and further comprises a core control module, an AHB system bus decoding module and a register module; The register module is respectively connected with the sending buffer area, the receiving buffer area, the core control module and the AHB system bus decoding module, and is used for storing data from the receiving buffer area, the core control module and the AHB system bus decoding module, and also used for storing control zone bits and status zone bits, wherein the control zone bits at least comprise direction identification bits for identifying the data transmission direction, and the status zone bits at least comprise data transmission completion zone bits for identifying whether transmission is completed or not; The AHB system bus decoding module is respectively connected with the core control module and the register module and is used for responding to the request of the chip CPU and executing reading or writing operation on the register module; The core control module is respectively connected with the SPI interface, the sending buffer area, the receiving buffer area, the register module and the AHB system bus decoding module, and is used for determining and calculating the length of sending effective data or the length of receiving effective data according to the direction identification bit in the control zone bit stored in the register module, detecting the level state of a chip selection signal output by the SPI interface in real time, acquiring the data quantity in the sending buffer area or the receiving buffer area in real time when the chip selection signal is detected to be low level, calculating the length of sending or receiving effective data and storing the length of sending or receiving effective data into the register module, setting the data transmission completion zone bit in the register module when the chip selection signal is detected to be high level, and resetting the data transmission completion zone bit in the register module according to the control signal output by the AHB system bus decoding module. According to a second aspect of the present invention, there is provided a chip comprising the above-described SPI slave controller, the chip communicating with a host through the SPI slave controller.